Reviewing
the comparison data we see that the data measured and the data calculated
track within a 2% window below 35% dutycycle while delivering up
to 65 amps rms current to the inductive load as shown in GRAPH 
1. After 35% dutycycle the error between the data sets increases.
This error is mainly due to the MOSFETs Rds ON being set to a constant
6.0 milliohms in the analysis. Since the FETs RdsON increases
with temperature we should see a larger error window as the FETs
temperature increases due to the current drive to the load. This
is also shown in the graphs of the Thermal Stack and current drain
in the Bridge
Test System TDA where we can see a 30°C rise in less than 30
seconds for a drive current 60 amp RMS to the inductive load.
GRAPH  1 COMPARISON OF EMPIRICAL TO THEORETICAL
DATA FET ON RESISTANCE FIXED AT 0.006 OHMS
The FETs
that were used for this test are shown to have a 3 to 4 milliohm
change in Rds ON for thermal changes due to high currents. Knowing
this we adjusted the resistance of the FETs in the MathCAD file
to add a total of 4 milliohms to the FET ON resistance as we increased
the current.
As we can
see in the graphs below This simple adjustment brings us to within
a 2% error margin of the empirical and theoretical data sets.
This confirms the analysis methodology for simple inductive loads
and allows us to move forward to a complex load mechanism. We are
now ready to characterize 3Ø FET power module with the Bridge Test
System for simple inductive loads which was the intent of this TDA.
Comments on these articles are welcome via email JT.
As time permits I will put together the complete analysis of this
TDA in both MathCAD and MatLab format. As time permits discussions
of FET switching characteristics and inductive loading will be covered.
Since the inductance load in this TDA was small and the switching
frequency was high in does not mean in any way that we should not
be concerned. This will be discussed in a later TDA.
GRAPH  2 COMPARISON OF EMPIRICAL TO THEORETICAL
DATA FET ON RESISTANCE TEMPERATURE CORRECTED

Error Graph After FET Thermal
Correction

