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3  BRIDGETEST SYSTEMSUMMARY

3 BRIDGE TEST SYSTEM BLOCK DIAGRAM
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GENERAL SPECIFICATION AND CONCERNS OF THE  TEST SYSTEM DURING DEVELOPMENT

The construction of the prototype test system was a Rack 'N' Stack and scrounged equipment type build as are most test system development projects in the industry today. "Don't test it now, then troubleshoot it later".  Once this system was assembled and we obtained the first data, the importance of it was realized and I was able to build a second pass of the system with some design additions. One of the primary functions of a successful test system is the data acquisition section.  Most COTS data acquisition systems today meet or exceed the data collection speed requirements of a test system similar to the one in this TDA. However, as we mentioned before, software licensing in my opinion is a very important issue. Smaller data acquisition system manufacturers supply all the general data acquisition hardware needs along with some standard data collection software. Keep in mind however, that I have not found any company that meets all my development needs, and doubt if there ever will be one. The data acquisition industry is still maturing, and it is getting to a point that there is no need to purchase a very expensive fully created system when you are able to have the flexibility and especially the control to expand your own system to meet your company needs. Keep in mind that owning your own system and software corporate wide allows the best return on investment and far more flexibility.  What was purchased separately for this development project was the current sensors, custom thermocouples that were 5 to 10 mill diameter tips, the Platinum RTDs,  the 64 channel data acquisition card and the isolation amplifiers.  I used a couple of BASIL Networks designs back in the late 80's that I presented in one of seminars for the RMS to DC & Peak detector interfaces and the custom inductive load along with the sequencer.  More discussion on these devices will be later on in the TDA.

This test system requires a unique test methodology such that we have several types of sensors that require different data collection rates. The thought of running several computers collecting data at different rates and then trying to synchronizing them will easily turn into an unwanted burden, and becomes a greater expense to maintain. What we need is a data acquisition collection system that will allow us to collect data at different rates per channel or groups of channels all synchronized to a trigger. One attempt was to use two different PCI data acquisition cards in the same desktop computer, however synchronization and randomly skewed data collection appeared to be a more difficult problem to overcome. The way we performed the initial testing here is to collect the data all at once at the highest required data collection then sort the data in software. Since the data was put on disk, large files would not be a problem. We were only collecting data for short periods of time as well so the actual size of the files was not a concern. What was more important is that there were no random skew problems to deal with. The phase current is another unique area for the test system. This is where the True RMS to DC converter worked out well. The chips on the market today have a variable crest factor as well as signal conditioning. That along with the digital scope we are able to acquire data and import to our analysis package to complete the performance reports. The final costs of this system was much less expensive than purchasing a complete system and the software development went without much effort. The following table lists out the purchased hardware and some of the specifications.    Top

DATA  ACQUISITION  CONFIGURATION  REQUIREMENTS

CHANNEL IDENTIFICATION

NUMBER OF CHANNELS

RATE  Samples/Sec

Resolution

SYNC

Thermocouple Type "T"   Temperature Sensors

16

2000

0.1

YES

RTD  Platinum 100 ohm 0.385 resistance to temperature ratio

32

2000

0.1

YES

Current Sensors, 0-200 amps DC, 100 KHz bandwidth,
Peak, rms and DC outputs, 010Volts, 05Volts output range.

8

DC to 500,000

0.001

YES

 

 

 

 

 

INSTRUMENTATION  CONFIGURATION  REQUIREMENTS  (COTS)

EQUIPMENT DESCRIPTION

NUMBER OF CHANNELS

RATE Samples/Sec

Resolution

SYNC

Digital Oscilloscope with data storage Tektronix, 754 series

4

DC to 500 MSPS

8 bits

YES

Power Supply, DC to 200 Volts, 0 to 200 Amps Programmable

1

100 ms program response time

0.01 amps

YES

 Data Acquisition Card

64

 300,000

 16 bits

 YES

A few details about the test system instruments that are concerns. When we were looking for high current power supplies there were many of them to choose from, unless that is, if all you needed was high current. There were not many 100 Volt, 200 Amp programmable that were able to be turned off/on digitally. That is that fell into a reasonable price range. At the time of this development we had access to a custom designed 400 amp IGBT liquid cooled switch with a TTL gated control line and it was used for this application. There are a few companies that make these liquid cooled devices and they seem to be perfect for gating hundreds of amps. Another concern was the thermal monitoring system, since we were measuring the temperature on top of a FET die  that had bond wires on it and was about 1/4 inch square, with only had a few seconds at the most to take data. Using the small "T" type thermocouples and the fast signal conditioned isolation amplifiers allowed a data collection rate of better than 15 milliseconds /캜 response time. These 10 mil tip thermocouples are available from several manufacturers and are not very expensive. The Platinum RTDs were used to monitor the surface of the heat sink, ambient and other environmental temperatures around the module under test.

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GENERAL SPECIFICATION AND CONCERNS OF THE  SEQUENCER INSTRUMENT DURING DEVELOPMENT

The sequencer instrument is a product that I developed at BASIL Networks several years ago and just keeps on popping up with new applications. The key to any device of this type is the ability to deliver high speed digital signals in the 5 to 10 ns period range. The successful design will incorporate high frequency layout rules that are directly related to the designers packaging. Hence: change the packaging changes the design and layout.  The sequencer is basically a cache memory controller with the data ports feeding the real world, sounds simple enough, though, many tried few succeeded at a high cost.  Designing an accurate 200 MHz pipeline counter without the prop delays getting in the way is a little bit easier today with CPLD's but they still require some know how.  There have been some changes to this design to accommodate the testing of the bridge circuit and driving the modules six switching devices.  Driving High-Low MOSFETs required the design of a isolated drive circuit to insure that the threshold voltage, (Vth) is guaranteed. The other additions is the OFF State latch. This latch is basically a holding current latch for all three phases which will turn the devices on to a certain current level in each phase and not change. That is to say it will PWM to a specific point on the wave form being generated and remain in that state. The summary page will explain this in more detail.  The addition of a multiplexor was added to allow multiple PWM patterns to be switched in/out for comparing different PWM schemes without changing the test setup. Memory expansion is not as important today as it was 10 years ago. The density of high speed cache is now in the 36 meg bit (2Meg x 18 bits,  1Meg by 36 bits) and have speeds in the 3.5 to 10 ns range and are much less expensive.  The addition of a few timers for controlling the on/off intervals of the PWM waveform without the need for processor support, allows this device to free run and generate synchronization signals for other instruments. We selected this sequencer to control the triggering of all other attached devices because this is where the main bridge control signals are generated and monitored by the attached control computer. Also added was an external connector allowing the user to design and attach their own bridge driver design.

This design has taken several forms of the past several years, from dedicated Open Bus Interface Architecture (OBIA), to an ISA interface. I am looking into a USB design as a stand alone instrument that if any one is interested they should contact me JT for product specifics. This design generally travels with me from contract to contract requiring a fast system development.

3 BRIDGE TEST SYSTEM  -  SEQUENCER INSTRUMENT SECTION BLOCK DIAGRAM
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To explain the actual application and some of the limitations of PWM generation and control, we will look at the default setting of this system. To start we look at the memory width as an eight bit playback state per point. That is each address has eight bits that are programmable to any state. The memory's depth is 18 bits allowing 262,144 locations. The playback system is controlled by a final address register allowing playback control from a start location to a final location. The direction is also controlled as from a final location to a start location or from a start to the final location, hence bi-directional. The maximum rate at which the eight bit width is played backed at is determined by the speed of the memory chips, in this case it is 10ns, 100MHz. The new design is capable of  a 5 ns, 200 MHz playback rate and the latest proprietary designs have rates of up to 1ns. The playback is programmable up to the highest speed via a playback register. Now how does all this apply to the bridge module and PWM ? A detailed explanation is also given in the Test System Presentation PDF file (4 Meg file) downloadable from the first page of this TDA.,  A simple explanation is as follows. A simple sinewave may be generated as Asin(). Where "A" being the amplitude from min to max and being the angle from 0 to 360.  Now what we would like to do is control the amplitude "A" for any point on the 360 period. Since we are generating this waveform digitally the amplitude resolution of each point along the X axis is determined by the number of steps we are able to resolve its amplitude "A" to. If we use 10 steps then we will have 10 unique amplitudes to relate to which is represented as A(i)/10 * sin(). where i=0,1...9.  This covers the amplitude section. Now if we are to break the X axis up into 360 steps then we would get 1 per digital point. that would be resolved to an amplitude of one part in ten. Looking at this we see that we may get the same vertical value for several points on the sinewave, giving us almost a stepped waveform.  When we apply this to an motor as explained in the PMB DC Motor analysis this becomes a performance issue. Our default values of this test setup are 1000 parts for the vertical "Y" resolution and this number determines the number of points for the X axix. This means that for every X point we would require 1000 points to determine the Y value for a PWM point. Since we are controlling the FETs driving some sort of load configuration, the PWM point only supplies the power to the load for the number of pulses that resolve the vertical "Y" amplitude from 0 to 1000 pulses that set 0 to 100% of the point. The amplitude of the waveform becomes the duty cycle/   Each point is in this case is 1000 addresses wide allowing the FET to be turned to deliver power to the load in 0.1% steps. What does this mean in terms of maximum waveform period ? Well, if we playback the memory at 50 nanoseconds per address, and there is 1000 address per point then each point would be at 50 microseconds. Since this design uses only 265,144 locations, a 260 point waveform fits into the memory easily. This yields 260 points at 1000 steps vertically for each point for a total of 260,000 addresses. Playing this back at 50 nanoseconds per address then the total sinewave period is 260,000 * 50 nanoseconds or 13 milliseconds, 76.923 Hz. Applying this to a PMB two pole motor we would get a maximum speed of 4615 RPM. If we lowered the vertical resolution we would be able to increase the RPM. for a 10ns playback rate this system is capable of a 2.6 millisecond period, 384.615 Hz. therefore applying this to a six pole PMB motor we would get a maximum speed of 7692 RPM, (60* 384.615 / 3) This would allow the motor to be tested at any speed up to the maximum. or drive reactive loads as transformers for digitally controlled 3 variable voltage and variable frequency power supplies. I will be adding a section on PWM generation and analysis as time permits explaining how to mathematically optimize the vertical and horizontal resolutions for the best performance for the application. Now that we explained this with the least of mathematics, the PMB Motors  TDA will explain more of the theoretical analysis using MathCAD for this application.

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EIGHT CHANNEL DC TO RMS AND PEAK DETECTOR CIRCUIT

Measuring the PWM load current of an inductive load along with any strange peaks that may occur as well as the RMS values has always been interesting to say the least. To start with I collected data at a relatively fast rate in comparison to the playback period of 13 milliseconds. For this test I used both very expensive current probes and inexpensive COTS hall effect current modules.  The modules specifications guaranteed a full scale frequency response of 60KHz at 100 amps which when tested turned out to be within 0.5%  vertical accuracy and a frequency response beyond 100KHz and beyond that for small 10 amp transients at 80 amps base line. The hall sensors used had a 3 MHz bandwidth and the amplifier was the main limiting factor with a 1 MHz unity gain bandwidth. If I were to design one today I would expect the highest bandwidth that could be manufactured  These sensors produced a DC voltage of 5Vdc full scale for the 100 Amp device, 20 amps per volt. and 10 Volts for the 400 Amp device, 40 amps per volt.  Our data acquisition system  that sensed the current was capable of 300,000 Samples / Second at 16 bits vertical resolution along with a programmable gain amplifier per channel. This allow us to resolve around a 1 milliamp at 100 amps, well within anything this application would require. Measuring peak and rms levels were done in hardware and not software to maintain a single data collection rate for all the testing as well as making the data collection simple. We used a 500 MHz bandwidth digital scope to monitor transients and load current as shown in the summary.  A dedicated system for this field would be an asset to the future advances in PWM power drivers and we would be interested in advancing this field of interest. BASIL Network offers its expertise in the system development services in this area for those interested.

 

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