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IBPD System I²C Protocol Technical Overview
The I²C protocol is separated into two section, The I²C BUS Controller and the I²C BUS Slave.  The I²C BUS Protocol Dialog below allows complete control of the I²C BUS and send/receive data to any I²C slave device attached to the BUS.  

The I²C Slave will only take commands from an I²C BUS Controller.  In order to fully implement the I²C Protocol development we require both a slave and a Controller to function independently of each other.  The I²C Slave software is executed in a separate task in memory and is independent of the I²C Controller functions.  This allows the user to setup several I²C Controllers and Slave device simultaneously through the I²C Main Menu.  For advanced development the IBPD System Model-200 is used that incorporates a unique high speed serial/ serial-paraller BUS protocol for custom high speed protocol and security development, the Slave Devices have been removed from the Model-200 controller. The release is scheduled 3rd Qtr 2016

Since the Internet is full of I²C documentation some copied right out of the original developers manuscript for the protocol, we decided not to reprint this.  The complete I²C Specification and User Design Requirements are available for download in a single PDF by the creators of the I²C BUS, Phillips, now NXP.    Over the years the typical 1Kbit and 2Kbit devices have grown to 2 Mbit devices (256Kx8).  This increase also comes with a programming price as manufacturers compete to control a market segment.  This leaves the design engineer with a huge supply chain management issue for reliability and availability.  Many I²C devices regardless of whether they perform a peripheral function or just plain memory all follow conventional memory addressing formats for accessing internal registers or memory locations.  There are also custom I²C devices that do not follow any of the recommended conventional addressing schemes and requires special programming to incorporate these devices.  The IBPD-SYS I²C Slave protocol allows the emulation of both conventional and custom addressing devices and handle all the handshake requirements through easy to use dialogs that address all functions of the I²C protocol for a slave device.  The following is a brief overview of the I²C Slave protocol for various device. addressing methodologies implemented from small (128bit) to large(2Mbit) I²C devices; Extracted from the I²C Specifications from Phillips Spec UM10204 4 April 2014.

Group A = (1 0 1 0) [Bits 7..4]

Bit 3

Bit 2

Bit 1

NXP Device Type

Description of Device Type

0 0 0

PCB2421

1K dual mode serial EEPROM

0 0 0

PCB8583

Real-time clock calendar

0 0 1

PCB8563

Low-power clock calendar

0 0 1

PCB8593

Low-power clock calendar

A2 A1 A0

PCF8570

256 x 8-bit static RAM

A2 A1 A0

PCF8522/4

512 x 8-bit CMOS EEPROM

A2 A1 A0

PCA8581/C

128 x 8-bit EEPROM

A2 A1 A0

PCF8582/A

256 x 8-bit EEPROM

A2 A1 A0

PCX8594

512 x 8-bit CMOS EEPROM

A2 P1 P0

PCX8598

1024 x 8-bit CMOS EEPROM

B2 P1 P0

Multiple Devices

2048 to 512K x8 EEPROMS

The I²C Slave device requires a controller to activate the device before any data is transferred.  The illustrations below use the following block IDs to determine slave from controller.

I2C_Start Start Sequence from I²C Controller

Device_Select Physical Device Address from Controller

I2C_ReStart ReStart Sequence from I²C Controller

MemoryCell Memory Cell Address From Controller

I2C_ACK Acknowledge data bit 9 from the device

Device R_W Read / Write Control Bit from Controller

I2C_Stop Stop Sequence from the I²C Controller

DataBit Device Data Bits

The typical I²C memory device allows both single and page read and write functions. The page size is dependent on the device size and custom manufacture parameters.  The simpler of devices are those that are less than or equal to 256 bytes (<2KBits.). Devices up to 2KBits only require an eight bit physical address to access all locations in the device, therefore the three remaining address lines in the control word are used for selecting one of eight physical devices on the I²C BUS.  Devices Greater than 2KBits(>256x8) and less than 4KBits(512x8)  use the A0 bit for the A9 address bit and the remaining bits in the control byte (A2, A3) are used for physical device select lines allowing up to 4 device on the BUS.  The 8KBit (1024x8) uses an additional address line A2 therefore only allowing one additional physical chip address A3.  Devices 32Kbits and above are addressed via a two byte address which allow a 3 bit physical address enabling up to eight physical chips on the BUS.,

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Banner_I2C_Slave_7_Bit_Addressing

Typical 7 bit addressing mode for devices up to 256x8 (2KBbits).

I2C_Device_8_Bit

 


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Typical 10 bit addressing mode for devices greater than 2kBits and Less than 8KBits(1048x8)

Banner_I2C_Slave_10_Bit_Addressing

 


Banner_I2C_Slave_16_Bit_Addressing

Typical 16 bit addressing mode for devices equal to or 256KBit (32Kx8) up to 512KBit (64Kx8).  The full 16 bit address is initiated by sending two address bytes then data for a single write access to a cell.

Banner_I2C_Slave_16_Bit_Addressing_Single

Page access sequential writes allow for faster programming times by sequentially writing 128 bytes at a time as shown below. For most devices of this size the page size is 128 bytes.  The starting address is on 128 byte boundaries for each page. This device also allows up to eight physical devices on the bus that are selected via the A2..A0 lines in the control byte.

I2C_Device_16_Bit_Address_Page

 


Banner_I2C_Slave_Above_16_Bit_Addressing

Typical 17 and 18 bit addressing modes for devices allow access equal to or greater than 1Mbit (128Kx8) up to 2Mbit (256Kx8).  The full 16 bit address is initiated by sending two address bytes for each 64K block in the device and the remaining one or two address bits are incorporated in the control word A0 and A1 these now become P0 & P1 for page select. This adds up to 18 bits total and the remaining A2 bit is for an additional 2Mbit device.  If the 1Mbit device is used only one additional page is require to access 128Kx8 cells therefore upt to four additional devices may be placed on the bus and selected using the A1 and A2 lines.

Typical 17 bit address device with provisions for an additional 4 devices using A2 and A1

I2C_Device_17_Bit_Addressing_Single

Typical 18 bit address device with provisions for an additional device using A2.

I2C_Device_18_Bit_Addressing_Single

Page access sequential writes allow for faster programming times by sequentially writing 128 bytes at a time as shown below. For most devices of this size the page size is 128 bytes.  The starting address is on 128 byte boundaries for each page. This device also allows up to eight physical devices on the bus that are selected via the Address 17, 16 lines in the control byte and the physical device is selected by A2..

I2C_Device_18_Bit_Addressing_Page

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