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I²C Patent & Legal Information - Phillips Corporation
Since October 10, 2006, no licensing fees are required to implement the I²C protocol controller.  However, fees are still required to obtain I²C slave addresses and Manufactuirer IDs allocated by NXP.

IBPD System I²C Protocol Technical Overview
The I²C protocol is separated into two section, The I²C BUS Controller and the I²C BUS Slave.  The I²C BUS Protocol Dialog below allows complete control of the I²C BUS and send/receive data to any I²C slave device attached to the BUS.  

The I²C Slave will only take commands from an I²C BUS Controller.  In order to fully implement the I²C Protocol development we require both a slave and a Controller to function independently of each other.  The I²C Slave software is executed in a separate task in memory and is independent of the I2C Controller functions.  This allows the user to setup several I²C Controllers and Slave device simultaneously through the I²C Main Menu.  For advanced development the IBPD System Model-200 is used that incorporates a unique high speed serial/ serial-paraller BUS protocol for custom high speed protocol and security development, the slave devices have been removed from the Model-200 Controller.  The release is scheduled 3rd Qtr 2016

Since the Internet is full of I²C documentation some copied right out of the original developers manuscript for the protocol, we decided not to reprint this.  The complete I²C Specification and User Design Requirements are available for download in a single PDF by the creators of the I²C BUS, Phillips, now NXP.    Over the years the typical 1Kbit and 2Kbit devices have grown to 2 Mbit devices (256Kx8).  This increase also comes with a programming price as manufacturers compete to control a market segment.  This leaves the design engineer with a huge supply chain management issue for reliability and availability.  Many I²C devices regardless of whether they perform a peripheral function or just plain memory all follow conventional memory addressing formats for accessing internal registers or memory locations.  There are also custom I²C devices that do not follow any of the recommended conventional addressing schemes and requires special programming to incorporate these devices.  The IBPD-SYS I²C Slave protocol allows the emulation of both conventional and custom addressing devices and handle all the handshake requirements through easy to use dialogs that address all functions of the I²C protocol for a slave device.  The following is a brief overview of the I²C Slave protocol for various device. addressing methodologies implemented from small (128bit) to large(2Mbit) I²C devices; Extracted from the I²C Specifications from Phillips Spec UM10204 4 April 2014.



The IBPD-Model-[1xx][2xx] MP[N]I²C controller incorporates both I²C and SPI and CPU Parallel Byte I/O for standard product development.  The basic hardware interface unit still supports the (Frequency Technology Devices Inc - FTDI  UM232H-B[NC][01] device for the BUS controller.  The Model-100 I²C controller allows devices to be programmed up to 4 Mb/s speeds which is the HS I2C Specifications,  however keep in mind that at the higher frequencies above 4 Mhz is non-standard and is outside of the specifications published for the I²C BUS.  Below is the Hardware timing requirements reference for the I²C protocol.  The Trigger/Sync pulses are incorporated in Models 100 and 200 controllers for development and testing and are timed with the start / stop specifications of the I2C BUS.  The IBPD System Model-200 controller (scheduled 3nd Qtr 2016) will allow the user greater flexibility with a modified serial bus interface for development of custom security protocols.  The timing diagram below is the standard I²C protocol for bothmodels 100 and 200.  The sync/trigger lines are independent of the I²C bus operations and are available on separate terminals on the IBPD-Model-[1xx][2xx] MP[N]I² controller.

IBPD-SYS Models-[1xx][2xx][4xx]   I²C TIMING



The first byte of the I²C is the control and slave address byte. The first four bits (MSBit(7)..Bit(4) represent one of 16 groups assigned by the I²C specification.  The groups allocate specific functions for addressing slave devices and pertain mostly to NXP/Phillips devices, Download I²C Spec 4 Apr 2014 here.  For our examples we will use typical memory chips. If you are developing custom products that use the I²C bus a typical memory device control would be advisable unless your product falls into a specific group category that has already been assigned.  It is always recommended when developing new I²C slave devices to contact NXP for any licensing requirements.  Controllers are not required to be licensed, however depending on the application slave group addressing still may require a license from NXP.

There are several Reserved group control address that are reserved as shown below.

(C C C C    A3 A2 A1)   [Bits [ 7..4    3..1 ]

Slave Address

R / W  Bit


0000  000


General Call Address

0000  000


START Byte ²

0000  001


CBUS address

0000  010


Reserved for different BUS format

0000  011


Reserved for future purpose

0000  1XX


Hs-Mode Master Code

1111  1XX


Device ID

1111  0XX


10 Bit Slave Addressing

  1. The General Call address is used for several fundctions including Software Reset
  2. No Device is allowed to acknowledge at the reception of the Start  byte
  3. The CBUS address has been reserved to enable the inter-mixing of CBUS compatible and I²C-bus compatible devices in the same system. I²>C-bus compatible devices are not allowed to respond on reception of this address

April 4, 2014 Manual Release Rev 6.

Manufacture Bit Assignment  ID  
11 10 9 8 7 6 5 4 3 2 1 0 Company
0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors

0 0 0 0 0 0 0 0 0 0 0 1

NXP Semiconductors Reserved

0 0 0 0 0 0 0 0 0 0 1 0

NXP Semiconductors Reserved

0 0 0 0 0 0 0 0 0 0 1 1

NXP Semiconductors Reserved

0 0 0 0 0 0 0 0 0 1 0 0

Ramtron International

0 0 0 0 0 0 0 0 0 1 0 1

Analog Devices

0 0 0 0 0 0 0 0 0 1 1 0

ST Microdevices

0 0 0 0 0 0 0 0 0 1 1 1

On Semioconductor

0 0 0 0 0 0 0 0 1 0 0 0

Sprintek Corporation

0 0 0 0 0 0 0 0 1 0 0 1

ESPROS Photonics AG

0 0 0 0 0 0 0 0 1 0 1 0

Fujitsu Semiconductor

0 0 0 0 0 0 0 0 1 0 1 1


0 0 0 0 0 0 0 0 1 1 0 0


0 0 0 0 0 0 0 0 1 1 0 1




Bit 3

Bit 2

Bit 1

NXP Device Type

Description of Device Type

0 0 0


1K dual mode serial EEPROM

0 0 0


Real-time clock calendar

0 0 1


Low-power clock calendar

0 0 1


Low-power clock calendar

A2 A1 A0


256 x 8-bit static RAM

A2 A1 A0


512 x 8-bit CMOS EEPROM

A2 A1 A0


128 x 8-bit EEPROM

A2 A1 A0


256 x 8-bit EEPROM

A2 A1 A0


512 x 8-bit CMOS EEPROM

A2 P1 P0


1024 x 8-bit CMOS EEPROM

B2 P1 P0

Multiple Devices

2048 to 512K x8 EEPROMS

The I²C Slave device requires a controller to activate the device before any data is transferred.  The illustrations below use the following block IDs to determine slave from controller.

I2C_Start Start Sequence from I²C Controller

Device_Select Physical Device Address from Controller

I2C_ReStart ReStart Sequence from I²C Controller

MemoryCell Memory Cell Address From Controller

I2C_ACK Acknowledge data bit 9 from the device

Device R_W Read / Write Control Bit from Controller

I2C_Stop Stop Sequence from the I²C Controller

DataBit Device Data Bits

The typical I²C memory device allows both single and page read and write functions. The page size is dependent on the device size and custom manufacture parameters.  The simpler of devices are those that are less than or equal to 256 bytes (<2KBits.). Devices up to 2KBits only require an eight bit physical address to access all locations in the device, therefore the three remaining address lines in the control word are used for selecting one of eight physical devices on the I²C BUS.  Devices Greater than 2KBits(>256x8) and less than 4KBits(512x8)  use the A0 bit for the A9 address bit and the remaining bits in the control byte (A2, A3) are used for physical device select lines allowing up to 4 device on the BUS.  The 8KBit (1024x8) uses an additional address line A2 therefore only allowing one additional physical chip address A3.  Devices 32Kbits and above are addressed via a two byte address which allow a 3 bit physical address enabling up to eight physical chips on the BUS.,


Writing to devices that have less than 8 bit addressing and storage only requires single byte operations to perform the read or write.  Many of these devices have a page mode read/write of 8 byte blocks. Single write operations require a write time delay for the device to write each address selected. The time required to write the entire device is (Device size) * (Write Delay).

Typical 7 bit single write EEPROM addressing mode for devices up to 256x8 (2KBbits).


Page access sequential writes allow for faster programming times by sequentially writing  8 bytes for smaller devices  and up to 128 bytes at a time for larger capacity devices as shown below.  For most devices the size the page buffer ranges from 8 to 128 bytes and is dependent of device capacity.  The starting address is on the page size boundaries for each page. The device addressing shown allows up to eight physical devices on the bus that are selected via the A2, A1,A0 lines in the control byte.  These bits are internally compared in the device and the devices pins are hard wired to high or low to select the physical address.  The programming size is reduces by a factor of the page size since the page is burned in at one time, therefore reducing total write time.

Typical 7 bit Page write EEPROM addressing mode for devices up to 256x8 (2KBbits).



Typical 10 bit addressing mode for devices greater than 2kBits and Less than 8KBits(1048x8)
The Control Bits are changed to 1111 for 10 bit addressing for these devices. These devices will only
address one additional physical device that is enabled with address line A2.



Typical 16 bit addressing mode for devices equal to or 256KBit (32Kx8) up to 512KBit (64Kx8).
The full 16 bit address is initiated by sending two address bytes then data for a single write access to a cell.


Page access sequential writes allow for faster programming times by sequentially writing 128 bytes at a time.
For most devices of this size the page size is 128 bytes.  The starting address is on 128 byte boundaries for each page.
This device also allows up to eight physical devices on the bus that are selected via the A2..A0 lines in the control byte.



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