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PMGM130
SoftwareOverview

 

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PMG-130PMG-M-130
 
SoftwareSRAM SetupSRAM I/ODATA XferDevice SelectMulti-Freq PSKSimple  PSKPerformanceCommand Line Call

Software Specifications

System Requirements

Operating System

Windows 8 [32/64]
Windows 7 [32/64]
Windows-XP SP2 or above 32Meg RAM for single application.
Windows-2000- Service pack 3 or higher

Display

VGA 256 colors 1024x768 minimum, Recommended 1280x1024 or higher with 16 bit color.

Devices & Drivers

Number of PMGMs per System

1 to 255 PMG-M-130 PCI / PXI cards per system BUS.  1 to 255  systems

List Boxes

SRAM I/O Transfer List  
SRAM File Load List  
Create Command-File List
Device Select List
Filenames
SAVE SETS

The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 255
The max length of a filename including the path is 255
Limited only by disk size

Internal Calculations

Frequency A, B, Delta & Ref
Update Timer
Phase
Amplitude I & Q
Offset I & Q

64 bit double precision floating point to 48 bit integer truncation
64 bit double precision floating point to 32 bit integer truncation to 14 bit integer
32 bit single precision floating point
32 bit single precision floating point to 12 bit integer truncation
32 bit single precision floating point to 12 bit integer truncation

User SRAM  PMG-M -130

Serial Bit Stream Modulation
Transfer Type
User Area Size
Configuration


USER SRAM
User Area Size
Configuration Data I/O

Four Channel - Byte Load - 4 bit nibble transfer, variable bit size 1 to 16 bits per word xfer.
Single transfer or Loop Back operation
0 to 258,047 (3EFFF hex) USER DEFINED IBR Addresses.
Block sequence of 0-255 (FF hex) consecutive IBR addresses
(255 random IBR address selection fields) 

Digital Data Transfer
0 to 258,047 (3EFFF hex) USER DEFINED IBR Addresses.
Block size of 1-258,047 (3EFFF hex) consecutive Data addresses

Word Recognition 8 Bit Standard

Standard Word Recognition
Sampling Control 
Outputs

8 bit CMOS Level Input from internal header connector
Internal 25MHz clock or External Clock via internal header
A=B, A>B, A<B Programmable to SMA PCI Connector

Word Recognition 32 Bit Option ( Separate Daughter Card )

Standard Word Recognition
Sampling Control 
Outputs
Programmable bit rate
Programmable bit size

USER SRAM

32 bit analog Input 50mv to 5volts 50MHz from separated PCI Slot Bracket
Internal 50MHz clock or External Clock via SMA connector, Sampling rates to 100MHz
A=B, A>B, A<B Programmable to SMA PCI Connector Digital pulse or latched
Programmable Bit rate divide by 2N when N= 1 to 16.
Programmable Bit size from 1 bit to 16 bits per word.

256Kx16 USER SRAM for serial data patterns

Modulation Control - Frequency and Phase Shift Keying

Standard FSK
Standard PSK

Internal headers

Selection from one of four for each channel
Selection from one of four for each channel

User iNternal Headers for Frequency and Phase Shift Keying inputs.
Standard LVTTL 3.3 volt, 5 volt tolrant inputs.

Help System
 

All Manuals in PDF format on disk for immediate reference

PMG-M-130 Software Overview

The PMG-M-130 Application software is a statically structured stand-alone software package. It has been designed to allow the user to execute several of the PMG-M-130.EXE programs simultaneously in a windows environment. This type of flexibility enhances the development of multiple PMG-M-130 devices installed in a single system.

The Functional Block Diagram, shown below, outlines the integrated components which control all the functionality of the PMG-M-130 hardware. The Program Navigation FlowDiagram relates the integrated components to the users interactive windows. The application program uses a global parameter area from which all the integrated components share. The MAIN Program Window is the link to all integrated sections of the program and ultimately program termination is from the MAIN Window. The following integrated sections make up the PMG-M-130 program.

Functional Navigation Block Diagram of the PMG-M-130 Application and Development Software

PMG-M-130  Main Program Window

The MAIN control window allows the user to access the entire array of integrated control windows as well as handle the majority of stand-alone features of the PMG-130.  The MAIN control window has been separated into 12 functional groups as shown below.  These groups will vary in functionality depending on the complexity of the changes in hardware required for the core modulation scheme selected.  Sections of each group will be deactivated when they are not available to help assist the user visually when programming the PMG-130.

As with all display windows the Windows Title Bar will contain the active device selected in brackets, [ N ] where N is the device number selected in the "Select Device" dialog.  The status bar in each window will display the results of the last command executed.

The MAIN Program window is partitioned in sections by function control of the PMG-M-130 hardware. Each of the following partitions of the main menu allow the user  complete control to configure the PMG-M-130.

MAIN PROGRAM MENU - These are the MAIN Dialog commands.

CHANNEL SETUP SELECTIONS - This is the channel setup dialog selection. Each button corresponds to the selected channel and the associated SMA connector on the PCI bracket.

PCI BRACKET LAYOUT - This is the SMA identification assignments as they appear on the PCI bracket

STATUS BAR OF LAST COMMAND - This is a monitor field for the status of the last command executed in the dialog.

On-Line Help Function - On-Line Help manuals.


MAIN MENU
The following is an overview of the menu system which allows the user to manually read/write to the SRAM directly.

EXIT PMG-M-130  - This function exits the main program.

Load Start-Up File - This allows the user to load a saved startup file.

SRAM I/O Transfer - This is the SRAM I/O transfer and configuration setup.

MODULATION INPUT SOURCE SELECTION - This is the MODULATION source dialog to set the MOD-IN and PHASE-IN pins source for each channel.

Data Transfer Setup  - This command activates the multi-channel Serial Data Transdfer options dialogs

Word Recognition - This command activated the 32 bit word recognition options dialog

Select Device - This command allows the user to select the device to be accessed, 1 to 255 devices are allowed

Start-Up Command File Creation  - This command displays the Creat Start-up Command File Dialog

Clear SRAM  - This command clears the On-Board SRAM.

STOP PMG-M-130 - This allows manual control of the SCAN Counter register

Transfer To Active Core - This allows manual control of the SRAM starting address of the scan

THardware Diagnostics Menu - This allows manual I/O control of the PMG-M internal registers for hardware troubleshooting.

The following sections of the PMG-M-130 Evaluation program are outlined below.  For the system Integrator, we have included all registers and their hex values for the software developer. There are source and library drivers available that may be used with C and WIndows Visual Studio along with applications of their use.  The C program library is compatable with all standard ANSI C and C++ compiliers.


CHANNEL 1 SETUP

PCI BRACKET Layout - This is the PCI bracket SMA connector layout for each signal. shows the signal labels for each channel.

CHANNEL-1 Setup - This will activate the Channel-1 Analog Output Dialog. Each channel has the same basic 27 hex (40 dec) IBRs along with the additional features IBRs for gain and offset for the output.

CHANNEL-2 Setup - This will activate the Channel-2 Analog Output Dialog. Each channel has the same basic 27 hex (40 dec) IBRs along with the additional features IBRs for gain and offset for the output.

SMA CONNECTOR CONFIGURATION  - This will activate the SMA Connector user configuration dialog which will allow the user to select the desired signal to be placed on the MA connector. For OEM's this is a custom design option based on the actual OEM features of the contract.

CHANNEL-3 Setup - This will activate the Channel-3 CLOCK Output Dialog. Each channel has the same basic 27 hex (40 dec) IBRs along with the additional features First for Update Source Select, Standard 8 bit Word recognition, Phase and Frequency Modulation input selections.

CHANNEL-4 Setup - This will activate the Channel-4 Phase Lock Loop (PL) Output Dialog. Each channel has the same basic 27 hex (40 dec) IBRs along with the additional features IBRs for the PLL Divider and the PLL control IBR.

TCXO Ref Clock Power - This will control the power tio the TCXO internal 50MHz reference. Default is ON

IDENTIFICATION of SMA Connectors

 

Channel 1 through 4 setup follows the same format as the single channel PMG-130 with a few more features. These features are unique to each channel and are factory configurable depending on the OEM requirements for the customer. Each channel of the PMG-M-130 has a common register set of 27 hex (40 decimal) registers that function the same for each channel.  The added function for each channel use the IBRs from 30 hex to 3B hex ( 48 to 59 decimal) as required for the functions added for that channel. IBRs 3C-3F (60-63 Decimal) are user defined for each channel. All other IBRs are reserved for product expansion and should not be used.

Modulation Core Type

The Core Modulation Selection allows the user to manually setup a modulation scheme from a pull down window.  When the user completes a menu selection the MAIN display will set all the parameters that are not used for the selected modulation type to read-only as a visual aid for the user, identifying the IBRs that are not used for this core mode. This isolates any parameters that are not available to the selected modulation type.  When the FUNCTION Select (from the MAIN menu area) is used to choose a modulation scheme, the Core Modulation Type is changed to reflect the selection when returned to the MAIN display. The diagram to the left shows the pull down menus and the available core modulation schemes.  Table 2.1.0, the Core Functionality Relationships to Modes of Operation in the PMG-130 software manual, outlines the parameters available to the user for each selected modulation scheme.  This table is useful to determine what IBRs must be accessed and controlled for user generated modulation schemes.

UPDATE TIMER SETUP

From our overview of the hardware we see that there are two sets of control registers that allow the user to setup the next state of the PMG-M while the current state is active. They are called the Active core and the holding registers. The Update Timer control allows the user to set a periodic update time resolved to 2/IntClk seconds when the internal clock is used. The external clock is controlled by the user.

TIMER SOURCE - The Update Timer source is EXTERNAL or INTERNAL. When the source is INTERNAL the timer input is the Internal Clock frequency IntClk. The counters controlling the IBRs automatically adjust to represent the correct update time when the Reference Clock is changed. When set to Internal it is used to update the active core with the data in the holding registers. When set to external the user has full control of the PMG-M active core and SRAM scan logic.

SET UPDATE TIME REGISTERS  - The Set Update Time button is redundant and performs the same function as the multiplier buttons. The User enters a time in decimal form and then selects the multiplier or pushes the Set Update Time button. This changes the Decimal and IBR Hex values displays.

ENTER UPDATE TIME PERIOD - The decimal time is entered here by the user. The time is automatically calculated based on the IntClk frequency setup by the user. When the Timer Source is set to External this group is disabled and the update pulse must be supplied by the user at the Remote I/O connector.

TIME ENTRY MULTIPLIERS - The Multipliers are used to set the update time from the value entered in the user entry area. This is a double precision floating point entry field and is truncated to a 32 bit integer.

IBR Hex DATA BYTES - This group of values display the IBRs used for the Update Time. These are read-only fields and area used as an IBR identification for setting up the SRAM뭩 user controlled modulation schemes.

UPDATE VALUE - 32 BIT DECIMAL - This value is a read-only display for user reference.

 

Frequency Registers Setup [ 120 MHz Max - 1.07 킜z Resolution
Figure 2.9.0  in the manual

The Frequency Control group is the main variable of the PMG-M-130 since we are dealing with various schemes to control groups of frequencies of a device. This group has four user interactive data areas for controlling frequency output of the PMG-M-130. There are three frequency control areas, Frequency A,  Frequency B and Delta Frequency and one rate control,  Delta Frequency rate change.  Frequencies A and B are used for Frequency shift keying allowing seamless frequency shifts from Frequency A to B as the MODIN Remote I/O control line state is changed.  The Delta Frequency and the Delta Frequency Rate are used for modulation schemes that require incremental frequency steps at a selected rate which are detailed in the hardware manuals Theory of Operation.  All data areas have an associated Internal Behavioral Registers (IBR) displayed in HEX format.  The HEX data and the associated IBR are stored in the SRAM reserved area and identify the current PMG-M active state that the user may set by pressing the TRANSFER PMG-M ACTIVE button in the Menu Selection Group area. Each of the displayed hex IBR areas are updated in real time in the display area only as the USER data areas are changed.  The PMG-M-130 current state will only be changed to reflect the displayed when the user updates the PMG-M by pressing the TRANSFER PMG-M ACTIVE button.  Prior to that the data is stored in the IBR holding buffer until ready. All Frequency ranges are from DC to 130 MHz with 1.0z Hz resolution.

FREQUENCY A - This is the main frequency that is connected to all modes of operation. For single frequency mode this setting is present at the I & Q outputs. When in the FSK type modes, this is the frequency that is present at the outputs when the MODIN pin on the Remote I/O connector is at a logic 0. The BYTE HEX VALUE IBRs 04-09 hex are the associated IBR addresses for the Frequency A decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

FREQUENCY B - This is the first support frequency that is connected to all the FSK modes of operation. When in the FSK type modes, this is the frequency that is present at the outputs when the MODIN pin on the Remote I/O connector is at a logic 1. The BYTE HEX VALUE IBRs 0A-0F hex are the associated IBR addresses for the Frequency B decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

DELTA FREQUENCY - This is the second support frequency that is connected to the RAMPED FSK and CHIRP modes of operation. When in the RAMPED FSK type modes, this is the frequency that the output ramps to when the MODIN pin on the Remote I/O connector is at a logic 1. The rate of the frequency change is determined by the Delta Ramp Rate value set by the user.  The BYTE HEX VALUE IBRs 10-15 hex are the associated IBR addresses for the Delta Frequency decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1.0 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

DELTA RAMP RATE - This is the frequency step rate that the RAMPED FSK will change when the MODIN pin on the Remote I/O Connector is changes from a Logic 0 to a Logic 1. The BYTE HEX VALUE IBRs 1A-1C hex are the associated IBR addresses for the Delta Ramp Rate decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 period of the IntClk frequency and the calculations are rounded to the nearest bit value as outlined in the Hardware Manual Theory of operation.

FREQUENCY A,B, DELTA IBR Hex Dat   - This group of displays are for the user뭩 reference when using the SRAM Sequence Programming control to develop custom modulation schemes. They represent the hex data byte associated with the IBRs address on the partition, hence: from the section Frequency A IBR 04 hex has hex 2A data assigned to it.

CLOCK REFERENCE CONTROL

The  Clock Reference setup allows the user to select the source of the reference source, INTERNAL or EXTERNAL. This is the main reference for all the PMG-M operations. This is where the Internal Clock (IntClk) is generated and connected to several PMG-M internal control groups of the design.  When in the INTERNAL mode, the PMG-M-130뭩 internal TCXO 50 MHz reference Oscillator is used and the PLL Multiplier is preset to 뱗6 to establish a 300 MHz Internal Clock (IntClk) frequency.  When in the EXTERNAL mode the user has complete control over the Internal Clock reference by setting the Reference IN values along with the PLL Multiplier.  The maximum limit of the internal clock is 300MHz and should not be exceeded. The Reference Clock Mux Switch allows the user to select the reference or each channel independetly from one of four sources, This allows the synchronization of all four channes from a user selected source.

PLL MULTIPLIER SELECT - The PLL (Phase Lock Loop) Multiplier is used as a  direct frequency multiplier to the Reference Frequency in at the REF-IN SMB Connector and is used to develop the Internal Clock Frequency.  Hence;  PLL Multiplier x REF-IN is the Internal Clock IntClk frequency and is displayed in  the Clock Setup frame for user reference. When the user select the INTERNAL mode this display is disabled to a read-only mode and set to 뱗6 yielding a 300 MHz IntClk.  

REFERENCE FREQUENCY IN  - This is the user supplied frequency reference connected to the REF-IN SMB connector number eight. When the user selects the INTERNAL mode this display is disabled to a read-only mode and set to 50,000,000.000 Hz.

INTERNAL CLOCK FREQUENCY - This display is always a read-only display and is computed from the PLL Multiplier settings and the Reference IN settings. When the user select the INTERNAL mode this display is disabled to a read-only mode and set to 300 MHz.

 

AMLPITUDE and OFFSET CONTROL

Channel 1 allows the user to control the amplitude and offset of the analog signal output. The output control has a 12 bit dynamic range and is adjustable over the +/- 4 volt output.

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