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SRAM_SETUP

 

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PMG-M-130 SRAM Sequence Configuration Setup and Control

The SRAM Setup and Configuration is the main user interactive window for developing new configuration schemes and activating them in a single pulse per frame mode.  This is one of the ATE features of the PMG-M-130 that allows the user to change the configuration with a single remote pulse without CPU intervention. After the single step mode is finished, the user may save the modulation scheme developed in a SRAM Saveset  and or load it directly to the SRAM on the selected device. SRAM Savesets may be of any size and may be loaded to any SRAM starting address. This allows the user to select portions of several SAVESETS maximizing reuse of existing frames.

The SRAM setup diagram below shows the parameters that are being set with the software. Each Frame may contain a user defined behavior by setting as many IBR as required for the controlled response of the PMG-M-130. Each frame may be activated sequentially via the digital control I/O inputs or randomly under software control.  An overview of the steps and the ease of which a new configuration may be created are shown below.  Keep in mind that the data in the TABs are retrieved from each channels fields, this allows the user to go to each channel and set the desired parameters for the test then simply click on the Setup SRAM I/O and start the process.

A brief overview of FRAMES and BLOCKS are shown below in order to visualize the concept of the flexibility of the PMG-M-130. There are a couple of conditions for using frames and blocks for this release. One, all frames in the block must be of the same size and may be from 1 to 255 bytes. Two, the Starting address must be defined under program control for the setup of the Frame. Both of these conditions are defined when you save the SRAM Saveset therefore are transparent to the user if the file defaults are used. The user may change the SRAM SaveSet files Starting address by setting the new SRAM Starting address manually in the SRAM I/O Transfer.

SRAM FRAMES AND BLOCKS ASSIGNMENTS

 

SRAM FRAMES, BLOCKS and PARTITIONS CONFIGURATION DIALOG

 

 SRAM FRAME Setup MENU - The SRAM FRAME Setup MENU group allows the Loading, Saving and Clearing for a new SRAM configuration scheme. The SRAM I/O Transfer allows the Saving and Loading of SRAM SAVESETS.

 SRAM IBR OPTION TABS GROUP - The TABS GROUP allows easy changing between channel IBR for creating random IBR frames.

 TAB SELECTED IBR's DISPLAY GROUP - The data associated with the selected  TABs IBR group is displayed for selecting random IBRs. This allows the user to visually see the data being stored for the selected IBR.

SRAM USERS SETUP GROUP- This is the USER selected area for custom applications. To use this area the user must have the External IBR extension option which allows the selective programming through a CPLD for each USER area associated with each Channels TAB.  The External IBR Extension is Write Byte pattern for Output through SRAM remote pulse control and Read only under Program control.  USER IBRs may be either Read or Write in any address order that are available.  

STATUS BAR - This is the Status bar that will display the status of each operation the user performs during this session.

IBR ADDRESS - SRAM RANDOM SEQUENCE GROUP - The IBR ADDRESS - SRAM RANDOM SEQUENCE group is where the users selects the IBR addresses to change when using the PMG-M-130 in REMOTE mode.  Depending on the options installed up to 255, (00-FF hex) IBR addresses are available to the user.  The user selects a sequential group of addresses along with up to 64 decimal (3F Hex) random IBR addresses to change.  The maximum frame size is 255 decimal (FF Hex) IBRs. Addresses displayed are all in hex format for this session.

 FRAME NAME - This field is for the current FRAME identification. It is not implemented in this release and is intended to help the user to keep track of the frames being created. In future releases it is intended to be implemented in the Runtime program for allowing the user to track the sequence process.

SRAM Navigation Menu Group

  RETURN - This button will return to the MAIN Display program. If any IBR store functions were executed, the current position and addresses are kept and a set of controls to continue the store IBRs are displayed on the MAIN DISPLAY. 

 NEW - This button will clear the SRAM buffer arrays and all associated variables for the SRAM to a known state for a NEW IBR block to be created.

 SRAM I/O Transfer - The SRAM I/O Transfer button brings up the SRAM I/O Transfer Window. This window allows the following functions to the selected PMG-M-130 device.

SRAM EBR Control Group Setup

The EBR, (External Behavioral Register) setup group is the starting point for all SRAM configuration activity. There are several data entry areas that allow the user to configure the SRAM addresses and view the SRAM data stored in the local SRAM buffer array.  All transactions to and from the selected on-board SRAM device are from the SRAM addresses set in this area.

 SRAM CURRENT ADDRESS - This is the Current SRAM address that will be used as a reference for the next 밪tore IBR Word or 밪tore IBR Group operation for the create SRAM mode. In the View Frame mode  this is the SRAM starting address of the current frame being viewed.  This address is automatically calculated after each Store or View operation executed.

 CURRENT IBR DATA & ADDRESS  - This is the current IBR address and associated data that will be stored to the SRAM Current Address field when the 밪tore IBR Word  button is pushed. It is also the last IBR window the mouse was clicked on.  In the read address mode, activated by entering an address in the 밪RAM Current Address field, it is the data associated with the entered 밪RAM Current Address field.

 STORE CURRENT IBR DATA & ADDRESS  - The Store IBR Word Button will store the IBR address and Data displayed in  Current IBR addr & Data fields to the SRAM address shown in the SRAM Current Address field.  After the store sequence is completed the SRAM current address increments and is ready for the next operation. This allows the user to build a frame with single IBR operations or to change a particular byte within a frame at random.

 SETUP VIEW  / FRAME VIEW  - The 밪ETUP View / 밊RAME View Toggle Push On-Push Off  Button allows the user to view between the PMG-130 current device settings and the Current SRAM buffer arrays selected Frame. The Frame reference is the address shown in the BLOCK Reference Address field.  Items  and  are also used to display the proper frame number selected.  The relative address is defined as:

View Frame SRAM Address = BLOCK Reference Address Frame Size View Current Frame Value

The SRAM Current address field is the starting point for the frame referenced from the beginning of the BLOCK Reference Address field.  The user may also change the current VIEW FRAME IBR data for those areas that are allowed and then transfer it to the PMG-130 active core to test the results. The user may also save the current VIEW FRAME by pressing the Store IBR Sequence button on the LOAD SRAM group area. Once in the Frame View the user may use the up-down arrow keys to increment-decrement through the frames or just enter a frame number to view.  The displays are automatically updated and the associated data displayed.

 FRAME TO VIEW ENTRY - This field selects FRAME to view when in the 밊rame View mode.

 SCAN COUNT ENTRY - This value is this field is the number of Scans the user wants to perform in the modulation scheme. It is an active window for decimal and hex displays. When the number is ready to be transferred to the current device,  the user will press the 밪et SCAN Cntr button.

 SET SCAN COUNTER - This Button will store the value displayed in the Decimal field to the Scan Count Register on the selected PMG-130 device.  This button performs an I/O Write to the Scan Counter EBR-04 .

 NUMBER OF FRAMES SETUP - The Number of Frames field is a reference for the user.  It is used to calculate the actual size and the number of IBR뭩 to be transferred.  If this is set to zero, then one frame will be setup when the user calls the SRAM TRANSFER Dialog. This field increments each time the 밪tore IBR Sequence on the IBR ADDRESS - RANDOM SRAM LOAD SEQUENCE setup area, (shown in Figure 2.23.0) is pushed.

 IBR FRAME SIZE - The IBR FRAMES Size is the number of IBR Bytes to be transferred during a remote operation each time a pulse is applied to the START pin on the REMOTE I/O Connector.  The data is either stored in the holding buffer and waits for an update pulse or the user may generate the update pulse at the last IBR address transferred to the holding registers.

 SET SRAM BLOCK START ADDRESS - The 밪et BLOCK Adr Button  will store the value displayed in the Decimal field  of the BLOCK Reference Address to the PMG-130 EBR-08. This button performs an I/O Write to the BLOCK Start Address Register EBR-08.  This allows the user to manually sequence through several modulation schemes (BLOCKS) stored in the devices on-board SRAM.

 BLOCK REFERENCE ADDRESS - The BLOCK Reference is the actual SRAM Start Address of the BLOCK of Frames for remote control of the modulation scheme.  This field is also used for the manual setup operations as well.

SRAM TABs  - IBR Hex Data Display

The SRAM IBR data display area is where we start programming the SRAM FRAMES and BLOCKS.  The display to the right is the standard display for all PMG-M-130 selected devices. This is the core IBR뭩 that the user has access to.  If other options are included then additional IBR TABS will be located in the TABS menu.  The user just has to click on an individual IBR display then move to the IBR ADDRESS - SRAM RANDOM SEQUENCE GROUP window and click on the field location (00-3F) where the IBR address is to be placed.  This process works for all IBR and the current TAB display area. The display area is automatically updated as each TAB is selected to the proper IBR addresses for that tab.  This allows the user to freely roam through the TABs to select the desired IBR and place it in the IBR Address - SRAM Random Sequence group for programming.

 

 TABS MENU for IBR OPTIONS - The TABS Menu defines the options installed in the device. The PMG-M-130 has several options which add TAB groups of IBR뭩 for users programmability.  The basic PMG-M-130 has four tab groups:

  • CHANNEL-1 IBRs' Analog - This may have single ended or Quadrature outputs
  • CHANNEL-2 IBRs' Analog - This may have single ended or Quadrature outputs
  • CHANNEL-3 CLOCK - This has a single sinewave out from 1 Hz to 130MHz  at 1 Volt Peak Several internal Squarewave pulses are available through headers for daughter cards and digital connectors on brackets for system synchronization.
  • CHANNEL-4 Phase Lock Loop - This channel has all the IBR required for he fractional PLL as shown in the IBR register layout

All options are accessed via byte wide IBRs' allowing user defined labels and data areas. This adds clarity for the applications.

 SELECTED TAB DATA DISPLAY AREA  - This is the display area for each TAB area displayed.  The user is free to move among the TABs to program the selected IBRs' when creating the FRAME.

 USER LABEL  ENTRY OPTIONS - The standard configuration allows eight user configured IBR labels and data for each channel.  The labels are limited to 15 characters per lIBR. This allows the user to configure the PMG-M-130 for specific applications that are clearly defined.

USER DATA ENTRY OPTIONS - The standard configuration allows eight user configured IBR byte wide data areas for each channel.  This data may be digital output data or digital input data that may be monitored under program control depending on the options selected.

SRAM IBR Random Load Sequence Setup

The IBR ADDRESS - RANDOM SRAM SEQUENCE Group allows the user to develop complex modulation schemes.  The group consists of a block of random address entry fields and one sequential group set,  밊rom - To fields.  The user may clear the group and start fresh without changing any previous group data saved.  The user may also store the group of IBRs in both areas to the local SRAM buffer array for later processing.  Once the IBR sequence is established the user may freely move from Dialog to Dialog window and change any parameters that effect the IBRs selected and store the results from MAIN or the SRAM Setup and Configure windows.

To use this group, the user just has to single click on any IBR display area in the TABs Display areas then move to the SRAM IBR random load sequence group window and click on the display area to place the address.  This will put the selected IBR address in that display area.  The user may repeat this process to develop the desired sequence.  The user may also select a group of windows the same way. Only the IBR address is placed in this group fields.  The IBR addresses and data are extracted automatically.  The current data and address are always displayed in the EBR Control Group window.

 CLEAR SEQUENCE - This button will clear the contents of the SRAM Load Sequence group. Any previous data stored in the local SRAM buffer array will not be affected by this operation.

 GROUP  IBR  SELECT  - This group allows the user to enter a contiguous set of IBR addresses. The user selects the start IBR address in the 밊rom and the Ending IBR address in the 밫o fields.

 STORE DISPLAYED SEQUENCE - This button will store the group of IBR addresses entered in both group areas to the SRAM Buffer array starting at the address displayed in the 밪RAM Current Address field in the SRAM EBR Control Group shown.  When in the VIEW FRAME mode, only the current frame being viewed is stored at the 밅urrent Starting Address field and is displayed. The number if IBR뭩 displayed is the value in the 밊rame Size filed.

FRAME NAME  - This is the frame name identifying the current frame being executed. This FRAME may be shown or hidden via a user command in the RUN TIME mode when the MAIN application program is running.  This is also used to help identify the sequence of frames when multiple frames are sequencing through a configuration.

 RANDOM IBR ADDRESS ENTRY - This is a block of up to 48 random IBR address entries the user may use for creating the modulation scheme application.  The user may select any IBR address at random and place it in this area.  The first blank area detected defaults to the end of the random IBR address sequence.  Since the update command transfers all the IBR holding registers to the active core at the same time, it does not matter what order the IBR addresses are entered to the holding registers. All transfers to the holding registers are at an 80 nanoseconds per address rate with a 20 nanoseconds end of transfer overhead.  As an example, six IBR addresses may be transferred in 500 nanoseconds.  For more information refer to the PMG-M-130 Hardware Reference, Manual Theory of Operation chapter.

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