BASIL_NETWORKS

PMG130

 

HomeABOUTPRODUCTSSERVICESSUPPORTCONTACTARTICLESBLOG
SystemsPeripheralsInstrumentsResearchNetworksSoftwareProgrammersOEM
PMG-130PMG-M-130
 
SoftwareSRAM SetupSRAM I/ODATA XferDevice SelectDigital OutputSimple  PSKMulti-Freq PSKQAMCommand Line Call

Software Specifications

System Requirements

Operating System

Windows-2000- Service pack 3 or higher
Windows-XP SP2 or above 32Meg RAM for single application.
Windows 7 [32/64]
Windows 8 [32/64]

Display

VGA 256 colors 800x600 minimum, Recommended 1024x768 or higher with 16 bit color.

Devices & Drivers

Number of PMGs per System

1 to 255 PMG-130 PCI / PXI cards per system BUS.  1 to 255  systems

List Boxes

SRAM I/O Transfer List  
SRAM File Load List  
Create Command-File List
Device Select List
Filenames
SAVE SETS

The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 500
The number of lines allowed in the list box is 255
The max length of a filename including the path is 255
Limited only by disk size

Internal Calculations

Frequency A, B, Delta & Ref
Update Timer
Phase
Amplitude I & Q
Offset I & Q

64 bit double precision floating point to 48 bit integer truncation
64 bit double precision floating point to 32 bit integer truncation to 14 bit integer
32 bit single precision floating point
32 bit single precision floating point to 12 bit integer truncation
32 bit single precision floating point to 12 bit integer truncation

User SRAM

Modulation
Transfer Type
User Area Size
Configuration

USER SRAM
User Area Size
Configuration Data I/O

Byte Load - 4 bit nibble transfer, variable bit size 1 to 16 bits per word transfer.
Single transfer or Loop Back operation
0 to 258,047 (3EFFF hex) USER DEFINED IBR Addresses.
Block sequence of 0-255 (FF hex) consecutive IBR addresses
(48 random IBR address selection fields)
Digital Data Transfer
0 to 258,047 (3EFFF hex) USER DEFINED IBR Addresses.
Block size of 1-258,047 (3EFFF hex) consecutive Data addresses

Help System
 

All Manuals in PDF format on disk for immediate reference

PMG-130 Software Overview

The PMG-130 Applications software is a statically structured stand-alone software package. It has been designed to allow the user to execute several of the PMG-130.EXE programs simultaneously in a windows environment. This type of flexibility enhances the development of multiple PMG-130 devices installed in a single system.

The Functional Block Diagram shown below, outlines the integrated components which control all the functionality of the PMG-130 hardware. The Program Navigation Flow diagram relates the integrated components to the users interactive windows. The program uses a global parameter area from which all the integrated components share. The MAIN Program Window is the link to all integrated sections of the program and ultimately program termination is from the MAIN Window. The following integrated sections make up the PMG-130 program.

The MAIN Program Window is the main link to all other interactive windows.  The MAIN window is usually the only window that has to be accessed for the non-remote simple operation.  As complexity increases other integrated windows have to be accessed.  The MAIN window and each of its components will be discussed in this chapter.

The Function Window allows the user to select a modulation scheme and also disables sections of the MAIN menu that is not used for the modulation scheme selected. As a support function the Remote Connection Help Window is used to show the user the Remote Connections Topology that is used with the selected Functions scheme.

The SRAM Configuration & Setup Window allows the user to easily program the Internal Behavioral Registers (IBR) that control the user generated modulation schemes.

The SRAM I/O Transfer Window is selected from the SRAM Configuration & Setup Window, and allows the user to transfer programmed data to and from the on-board SRAM.

The Device Select Window allows the user to switch between devices, independent of any current data that has been stored in the local buffers. When switching devices, no I/O data transfer takes place. This allows the user to control when a device is to be updated.  The current state of the device, that the user switches to or from, remains in the state prior to switching.  

The Create Command-File Window allows the user to create a Start-Up State command file for a selected PMG device.  The user has control of the Start-Up, Stop and SRAM states as well as several other programming functions.

The Data Transfer Window allows the user to control a block of 256K Bytes feeding it into the PMG Serial Modulation input while controlling the stop and start of the data from one bit to 16 bits in length. The Data I/O window also allows the user to transfer a single word transfer from 1 to 16 bits or a block of words with the ability to loop back and repeat the transfer from the on-board Data SRAM.

Functional Block Diagram of the PMG-130 Software

 

PMG-130  Main Menu

The MAIN control window allows the user to access the entire array of integrated control windows as well as handle the majority of stand-alone features of the PMG-130.  The MAIN control window has been separated into 12 functional groups as shown below.  These groups will vary in functionality depending on the complexity of the changes in hardware required for the core modulation scheme selected.  Sections of each group will be deactivated when they are not available to help assist the user visually when programming the PMG-130.

As with all display windows the Windows Title Bar will contain the active device selected.  The status bar in each window will display the results of the last command executed.

The MAIN Program window is partitioned in sections by function control of the PMG-130 hardware. Each of the following partitions of the main menu allow the user  complete control to configure the PMG-130.


MAIN Menu

The MENU Selection Control group, Figure 2.5.0, allows the user to access all the integrated dialog windows to control the PMG-130 device. There are eight sections to this group. An outline of each sections functionality is explained below. A detailed description will be presented in the sections to follow.

Functions - This menu selection invokes the Function Select Dialog Window. The Function Dialog displays the modulation schemes available to the user.

SRAM Setup - This menu selection invokes the SRAM Setup and Configuration dialog.  The SRAM setup is the main section to develop custom modulation schemes for the PMG..

Save Setup - This menu selection invokes the Save current configuration dialog as shown in Figure 2.6.0.  This only saves the IBR registers from 00-FF hex in a selected file. The default extension selected for this SAVESET is pmg.  This SAVESET may then be used to pre-load the PMG-130 device at start-up or for test systems as required.

Load Setup - This menu selection invokes a filtered file browser window with has a *.pmg standard filter allowing only PMG-130 acceptable files to be displayed. The user may then locate a configuration file previously saved with Save Setup  selection and load that file to the IBR holding buffers.

Data Transfer - This menu selection allow the user to setup the 256Kbyte data SRAM for transfering data to the PMG serial data input. The user can select data from a file generated from MatLab, MathCAD etc..

Stop Device - This menu selection sets the PMG-130 into a known idle state. The default is all power is turned off for the PMG core function and the Clock is disabled. The Output Control DACs are set to zero.  The user may also select a Default Stop state by setting the STOP = parameter in the Command Line at Start-Up or select the stop file in the Command-File Generation . The Command-Line and Command-File options are detailed at the end of this chapter.

Select Device - This menu selection invokes the Select Device Dialog window and allows the user to select the active device for access. Only the device installed in the current system will be displayed.

START-UP FILE - This menu selection allows the user to create a Command-File that will determine the start-up state of the PMG-130. The dialog with the user is just a point and click effort.

Transfer PMG Active - This menu selection transfers the IBR data from the holding buffer to the PMG Active Core. This is different from the Update Command from hardware. The holding buffer is in RAM and the holding registers are in the hardware. An Update command will transfer the holding registers to the active core. Therefore the Transfer button performs two functions, one, it transfers the IBR ram buffer array to the IBR holding registers; two, performs a software Update Command to transfer the holding register data to the Active Core.

Store Group - This menu selection only appears when the SRAM store is active. This is activated from the SRAM Setup dialog window. Once the SRAM store data has been setup and activated, transfers between the MAIN dialog and the SRAM dialog are enabled, thus, allowing the User to change any setting on the MAIN dialog window. The User can then press the Store Group Button to move next group of IBR data into the SRAM.

 

 

Modulation Core Type

The Core Modulation Selection allows the user to manually setup a modulation scheme from a pull down window.  When the user completes a menu selection the MAIN display will set all the parameters that are not used for the selected modulation type to read-only as a visual aid for the user, identifying the IBR뭩 that are not used for this core mode. This isolates any parameters that are not available to the selected modulation type.  When the FUNCTION Select (from the MAIN menu area) is used to choose a modulation scheme the Core Modulation Type is changed to reflect the selection when returned to the MAIN display. left shows the pull down menus and the available core modulation schemes.  See Table 2.1.0 Core Functionality Relationships to Modes of Operation in the software manual, outlines the parameters available to the user for each selected modulation scheme.  This table is useful to determine what IBR뭩 have to be accessed and controlled for user generated modulation schemes.

 

UPDATE TIMER SETUP

From our overview of the hardware we see that there are two sets of control registers that allow the user to setup the next state of the PMG while the current state is active. They are called the Active core and the holding registers. The Update Timer control allows the user to set a periodic update time resolved to 2/IntClk seconds when the internal clock is used. The external clock is controlled by the user.

TIMER SOURCE - The Update Timer source is EXTERNAL or INTERNAL. When the source is INTERNAL the timer input is the Internal Clock frequency IntClk. The counters controlling the IBR뭩 automatically adjust to represent the correct update time when the Reference Clock is changed. When set to Internal it is used to update the active core with the data in the holding registers. When set to external the user has full control of the PMG active core and SRAM scan logic.

SET UPDATE TIME REGISTERS  - The Set Update Time button is redundant and performs the same function as the multiplier buttons. The User enters a time in decimal form and then selects the multiplier or pushes the Set Update Time button. This changes the Decimal and IBR Hex values displays.

ENTER UPDATE TIME PERIOD - The decimal time is entered here by the user. The time is automatically calculated based on the IntClk frequency setup by the user. When the Timer Source is set to External this group is disabled and the update pulse must be supplied by the user at the Remote I/O connector.

TIME ENTRY MULTIPLIERS - The Multipliers are used to set the update time from the value entered in the user entry area. This is a double precession floating point entry field and is truncated to 32 bit integer.

IBR Hex DATA BYTES - This group of values display the IBR뭩 used for the Update Time. These are read-only fields and area used as an IBR identification for setting up the SRAM뭩 user controlled modulation schemes.

UPDATE VALUE - 32 BIT DECIMAL - This value is a read-only display for user reference.

 

 

Frequency Registers Setup [ 120 MHz Max - 1.07 킜z Resolution
Figure 2.9.0  in the manual

The Frequency Control group is the main variable of the PMG-130 since we are dealing with various schemes to control groups of frequencies of a device. This group has four user interactive data areas for controlling frequency output of the PMG-130. There are three frequency control areas, Frequency A,  Frequency B and Delta Frequency and one rate control,  Delta Frequency rate change.  Frequencies A and B are used for Frequency shift keying allowing seamless frequency shifts from Frequency A to B as the MODIN Remote I/O control line state is changed.  The Delta Frequency and the Delta Frequency Rate is used for modulation schemes that require incremental frequency steps at a selected rate which are detailed in the hardware manuals Theory of Operation.  All data areas have an associated Internal Behavioral Registers (IBR) displayed in HEX format.  The HEX data and the associated IBR are stored in the SRAM reserved area and identifies the current PMG active state that the user may set by pressing the TRANSFER PMG ACTIVE button in the Menu Selection Group area. Each of the displayed hex IBR areas are updated in real time in the display area only as the USER data areas are changed.  The PMG-130 current state will only be changed to reflect the displayed when the user updates the PMG by pressing the TRANSFER PMG ACTIVE button.  Prior to that the data is stored in the IBR holding buffer until ready. All Frequency ranges are from DC to 130 MHz with 1.0z Hz resolution.

FREQUENCY A - This is the main frequency that is connected to all modes of operation. For single frequency mode this setting is present at the I & Q outputs. When in the FSK type modes, this is the frequency that is present at the outputs when the MODIN pin on the Remote I/O connector is at a logic 0. The BYTE HEX VALUE IBR뭩 04-09 hex are the associated IBR addresses for the Frequency A decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

FREQUENCY B - This is the first support frequency that is connected to all the FSK modes of operation. When in the FSK type modes, this is the frequency that is present at the outputs when the MODIN pin on the Remote I/O connector is at a logic 1. The BYTE HEX VALUE IBR뭩 0A-0F hex are the associated IBR addresses for the Frequency B decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

DELTA FREQUENCY - This is the second support frequency that is connected to the RAMPED FSK and CHIRP modes of operation. When in the RAMPED FSK type modes, this is the frequency that the output ramps to when the MODIN pin on the Remote I/O connector is at a logic 1. The rate of the frequency change is determined by the Delta Ramp Rate value set by the user.  The BYTE HEX VALUE IBR뭩 10-15 hex are the associated IBR addresses for the Delta Frequency decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1.0 킜ertz and the calculations are rounded to the nearest 48 bit integer value as outlined in the Hardware Manual Theory of Operation.

DELTA RAMP RATE - This is the frequency step rate that the RAMPED FSK will change when the MODIN pin on the Remote I/O Connector is changes from a Logic 0 to a Logic 1. The BYTE HEX VALUE IBR뭩 1A-1C hex are the associated IBR addresses for the Delta Ramp Rate decimal value entered.  These addresses are used for the SRAM sequence programming. The entry resolution is 1 period of the IntClk frequency and the calculations are rounded to the nearest bit value as outlined in the Hardware Manual Theory of operation.

FREQUENCY A,B, DELTA IBR Hex Dat   - This group of displays are for the user뭩 reference when using the SRAM Sequence Programming control to develop custom modulation schemes. They represent the hex data byte associated with the IBRs address on the partition, hence: from the section Frequency A IBR 04 hex has hex 2A data assigned to it.

 

CLOCK REFERENCE CONTROL

The  Clock Reference setup allows the user to select the source of the reference source, INTERNAL or EXTERNAL. This is the main reference for all the PMG operations. This is where the Internal Clock (IntClk) is generated and connected to several PMG internal control groups of the design.  When in the INTERNAL mode the PMG-130뭩 internal TCXO 50.000,000 MHz reference Oscillator is used and the PLL Multiplier is preset to 뱗6 to establish a 300 MHz Internal Clock (IntClk) frequency.  When in the EXTERNAL mode the user has complete control over the Internal Clock reference by setting the Reference IN values along with the PLL Multiplier.  The maximum limit of the internal clock is 300MHz and should not be exceeded.

PLL MULTIPLIER SELECT - The PLL (Phase Lock Loop) Multiplier is used as a  direct frequency multiplier to the Reference Frequency in at the REF-IN SMB Connector and is used to develop the Internal Clock Frequency.  Hence;  PLL Multiplier x REF-IN is the Internal Clock IntClk frequency and is displayed in  for the users reference. When the user select the INTERNAL mode this display is disabled to a read-only mode and set to 뱗6 yielding a 300 MHz IntClk.  

REFERENCE FREQUENCY IN  - This is the user뭩 supplied frequency reference connected to the REF-IN SMB connector number eight. When the user select the INTERNAL mode this display is disabled to a read-only mode and set to 50,000,000.000 Hz.

INTERNAL CLOCK FREQUENCY - This display is always a read-only display and is computed from the PLL Multiplier settings and the Reference IN settings. When the user select the INTERNAL mode this display is disabled to a read-only mode and set to 300 MHz.

 

Copyright 1990-2018 BASIL Networks, PLLC. All rights reserved
webmaster