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PMG130
Digital_Expansion

 

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PMG-130PMG-M-130
 
SoftwareSRAM SetupSRAM I/ODATA XferDevice SelectDigital OutputSimple  PSKMulti-Freq PSKQAMCommand Line Call

The PMG-130 comes standard with an isolated control IO board containing two eight bit digital output registers.  For larger applications a simple interface using a 100 pin CPLD will yield an additional six - eight bit digital output ports ( 48 bits).  Incorporating a 144 pin CPLD would yield eight additional ports with pins to spare for additional control of the application. The expansion board may include optical isolation using TI's quad 25 Mb/s ISO SMT chips.  The digital expansion ports are included in the software and ready to be programmed without additional drivers etc.  Each SRAM IBR Tab in the SRAM Setup displays 32 user ports.  This opens the expansion of the PMG-130 limited only by the imagination.  The block diagram below shows a typical digital output expansion.

TYPICAL 64 BIT DIGITAL OUT EXPANSION BLOCK DIAGRAM

 

The following schematic block diagram uses Altera Quartus II with the EPM3128 100 pin TQFP showing a 6 byte port addition to the PMG-130. Digital out designs are normally limited to the number of pins of the connector along with the space available to place them. This design may be implemented on the applications main board using a single 18 pin ribbon cable from the PMG-130.

DIGITAL OUT EXPANSION USING ALTERA EPM3128ATC100-10  CPLD BLOCK SCHEMATIC

 

The PMG also includes a 32 bit Local Bus expansion connector for additional FPGA daughter card. The additional daughter card allows a data out and modulation controller to control a sequence of behaviors up to 65000 steps for a single pass or a programmed number of loops up to 232 -1 loops. The MAIN program Data Transfer button shows this screen. The Local Bus connectors are not part of the Digital expansion connectors.

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