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Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-22 | BASIL Networks Blog BN'B

10 Mar, 2021

Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-22

Part 22: IoT Core Platform Development;- Peripheral I/O Device Design
Updated Jan 25, 2022

The IoT Embedded Core Platform - Microprocessors & MicroControllers Update-
Peripheral Devices Real World Testing -

"People who are really serious about software should make their own hardware."  Alan  Curtis Kay ( May 17, 1940  )

As we stated in past presentations in this series, development costs are easily exceeded when the performance expectations and in that case performance requirements are not documented properly or, the infamous "TBD".  This forces a direction change "AND" direction changes are commonly not listed as part of  performance expectations.  Sometimes the development "process" is faulty or just plain broken period.  The intent of this series in not to maintain the insanity of over budget development costs but to disrupt it in order to allow the creation of new habits that will give a solid foundation for engineering practices to be successful when starting a development project.

For the new designer that is taking on the learning of CPLD and FPGA design, "Each design completed is experience for the next lever of development."  There are only experiences and techniques that will bring you to the advanced level of applications.

UPDATES  January 23, 2022
A lot has transpired over the past year with our research making the changes the world has had to face and rise above the challenges presented.  The industry globally has suffered he stress of productivity and here with this blog we have been absent for about a year as well.  So, starting the new year off and catching up this is an update on the project and the research being conducted.

IoT_Index Quick Links

Quick review to set the atmosphere for Part 21:
A full year has past since we posted on this IoT Platform Blog, to be fair, we were waiting for the dust to settle in the CPU arena to see who would win.  Well it is obvious that the ARM processor has won the battle at this time for the next platform.  Of course Intel will always be around and maybe it might even get the number one spot again.  Since the M&A of AMD and ARM the processor industry is undergoing a big change, Apple, Microsoft and others are moving over to the ARM processor architecture for software development.  Oh, by the way! the initial budget was exceeded as we will see in this part, BUT! for the better - of course.  alt 

So as of this writing here is what has been happening in the micro silicon world,   A couple of new embedded processors have emerged from all the Mergers & Acquisitions and many processors have been discontinued.  Performance and features such as higher core speeds and multiple cores make it applicable to many AI (Artificial Intelligent) applications.  Several interface ICs have been released that may help the interface along, however careful consideration has to be taken to insure that the interface will be around for at least five years to accommodate the embedded lifecycle requirements.

For review, the current Core Platform IoT development main focus is two fold, first an educational project development for the entrepreneurial mindset and the project applications of remote sensing and control incorporating safety, security and privacy over a wide range of peripherals including wireless.  This should be kept in mind since we will be designing in some redundancy for reliability and security.

The ITF development Project:
The ITF did create a change in direction, a change in budget and the project time line, however did not change the desired results, this is not only common in development projects but in some cases required to meet the desired expectations.  The delay for this blog was mainly due to the selection of the embedded processor that we will be using for the project.  Over the past two years there has been a lot of supply-chain management issues of embedded processors even though many supported the ARM processor they were all different in their interface capability which caused instability in the industry for selection.

The issues here still, are handling multiple projects, resources available and the changed timeline, just a short change in direction to complete the objective.  A validation that the real time product development process is far from being a linear process from conception to finished product.  That added with supply chain management to avoid redesign shortly after the product is release just creates uncertainty in the development cycle.  

To repeat,  Remember changing direction overnight does not mean changing goals our the final destination, it is just a better way to insure you will reach the desired destination.  With many years of exposure to the design arena as a designer, troubleshooter and mentor the honor of experiencing innovative and passionate creators has lead to the full realization that the creative thought process of an individual is not a linear step function, 1, 2, 3 ...N, probably because electro-chemical based humans are not programmable in the same way silicon based robots are that follow a preprogrammed set of processes, as some may think of engineers  The innovation of the human mind subconsciously is always creating and performing scenarios to find the best solution for the task at hand and "developing habits along the way".

What we want to cover in Part 22:
In Part-16 through 21 we addressed the issue of why we should consider testing of the peripherals (Proof of Design) PoD with a prototype build to insure when we interconnect several of the peripherals the throughput required for the applications will be met.  This allows the opportunity to change the development direction from the peripheral point of view if performance expectations become an issue. Developing a test methodology that will be used for testing peripherals for the platform keeping in mind peripheral throughput limitations. These are new habits being developed at a conscience mind set level that will connect to become the default critical thought process during development.  With that stated we will continue moving forward with detailing the Interface Test Fixture (ITF) CPLD #2.

Updating the IPD (Interactive Project Development) project documentation for the ITF (Interface Test Fixture) to keep track of the development process, "Documentation is a living process during development", a good habit to make!  The reference for the ITF is the functional block diagram Figure 16.1

Lets Get Started:
Some questions answered from our readers
"Again What happen to the series?,  "It has been almost a year from part 21, are you going to continue the series?  
To answer the above two questions - YES the series will continue.   What happened is simple a life TBD slipped in the process and adding a new blog to This IoT Platform Project that we were going to have to cover at some time so we were talked into doing it now, hence: the Wave Phenomenon, Antennas and Radiation blog was created. The blogs plus my daily responsibilities does not allow much if any time to get in trouble, yes, there are some that are happy with this situation.Cool   The main issue as we stated in previous parts was the selection of the embedded processor with respect to all the M&A's of the embedded industry reorganizing for the next generation of processor development, which appears to have shown some smoothing out, a direction with some major players for the next generation.  Here in the lab the past year has been actively creating some hardware and software for other parts of the blogs to give all interested some useful tools for this series that may also be applied to many other development projects as well.

What is next for the Embedded World
What is next in the Embedded Processor world, well, simple, Microchip, AMD, Intel, NXP, TI and a few others will be battling it out for a favorable position in the multi-billion dollar market place.  The merger of AMD and ARM will set the stage for the industry to move forward.  It is expected to see a new set of development tools for the ARM processor as well as a more robust series of cores.  AMD's ARM's M&A did catch a lot of attention for not only the embedded graphics market but also the desktop, Smartphone, and Tablet markets as well.

Keep in mind that all the M&A's are going to stabilize the market for a few years after the release of the new products that will identify the market niche's for each of the competing vendors.  The hobby market will see an influx of the older obsolete / discontinued processors that will be supported by some older software as the new cores are released.  Our IoT platform will be using the latest releases of cores to give at least a five year cycle if not more.   We will release the selection of the processors and why we chose them later in this part.

Changes In Supply Chain And M&A's:
OK, a lot has taken place in the past year with components and M&A's that have effected all manufacturers of the companies that used these components.  This is how it effected BASIL Networks Research, the IoT Core Platform blog development and with a little bit of a critical thought process other manufacturers of products that use the effective components.

To start a quick brief of BASIL Networks, 25 year experience dealing with Intel Corp Development group.  To cut the chase, Intel is well known for turning silicon every eight to 12 months and put the old silicon in "embedded or other market place department"   We presented this a few parts back about what happens with many M&A's and the products being discontinued.  

Discontinued Parts From the M&A
All this started with a PCN (Product Change Notice) in December 2020 from Intel Corp. discontinuing the entire MAX II line of CPLD's as well as over 500 other devices from several of the FPGA product lines.  OK, This is Intel's absolute right as a manufacturer to discontinue any product they want, when ever they want and when they want period.  The right of free enterprise, however there are always consequences to every action.  This is how it effected BASIL Network, PLLC and this blogs IoT Core Platform development series.  This is a great opportunity to document cause and effect of M&A's industrial changes.

Updated  Supply Chain January 23, 2022
OK, so last week I received a PCN from Intel regarding discontinued products - To my surprise Intel removed the Max+Plus II line of CPLD's from the discontinued list  PCN (Rev 2.0 1/23/2021-Product Change Notice) and extended the life to 2024 at which time the company will evaluate the status.  This was very good news to me since we have a couple of products in development and now we will have the opportunity to finish the development and get a few years service before a redesign.  The MaxII and MaxV product line have been at odds since the MaxV release, the big differences were the price and power. However the price made a small impact on older designs that still had a lot of life left for the cost of redesign kept the product as is. It would be an interesting task to see how many Last-Time-Buy orders were placed when the discontinuance notice went out.  

What is interesting is the number of M&A's over the past few years showing that the industry constantly evolves leaving a vast amount of excess inventory along with corporate structures that have to be evaluated.  This leads to reducing inventory to align with the new corporate direction and gives the surplus market an increase in inventory to sell off.  For our research and this blog is allows us to move forward with the development knowing that we will be able to support out research instrumentation build for a few more years.

Embedded Process industry expectations for over the past 20 years, Altera and others have kept the product line intact for the past 15 years well over the industrial standard of 5 years. This was great for small niche companies that were able to compete successfully.  The other companies that followed this path were Motorola, TI, AMD and many more.  Intel always paved its own path, however since the new major players are competing for a top level in the $40-$50 billion market of embedded changing and discontinuing silicon at a whim is no longer going to build the trust required to obtain this share.

The design used for the following test is the same design presented in this blog for high speed digital I/O direct to high speed memory which was designed back in 2001, yes a few years ago.

The Real Effects On Manufacturers
OK, some reality dealing with these changes!  For end user products that use MAX-II devices which there are many, however not as many as CPU's numbers, adding to that the fall in small businesses over the past two years due to lock downs etc. in those aspects the demand is low.  So no big deal just switch over to the MAX-V line which is still active and is a bit less expensive.  Well, it is never that easy to just switch components out these days and in this case this is what product designers and manufacturers have to consider.

As for this blog and the ITF, BASIL Networks, has enough part to build a few of the ITF for testing and use, however we will discuss this shortly.

Software Before vs Software Updated After M&A
Software is always a big issue when it is developed by different manufacturers to be used on the same product series, back to the opening quote.  I am not sure where the updated software for these CPLD/FPGA devices was developed and it did not really matter since it was from Intel Corp, until these tests were run.  For those of us that are able to program in VHDL if it compiles and runs with 30% less logic remaining then is should be consistent or close when moving from device to device in the same family; VHDL code is used in this design.  The majority of the complex blocks were compiled with the same VHDL code used with previous releases and followed the expected consistency of percentage used per family of chips.

OK, we discussed the new Intel Quartus Pro Lite CPLD, FPGA development software used a while back and it is time to update the software after a year or so.  Since this was a reuse design and developed with Quartus 9.1 which is way past its support life and also does not support MAX-V the we are now forced to use since the MAX-II is discontinued, the last release of Altera Quartus, 15.1 prior to the M&A was downloaded.  All still worked with both MAX-II and MAX-V as we will see below in the comparison table taken from the compilation report directly.  This design was saved from release 9.1 then copied to a separate directory, opened in release 15.1 and converted and compiled on the MAX-II with no changes, however on the MAX-V, the line "set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V" from the ADC_CHAN.qsf file had to be removed or changed to 1.8V for the MAX-V in order to allow for the 1.8 volt core voltage, we just removed the line as to be logic compatible.

As shown below in Table 22.0 below the compilation of both series MAX-II and MAX-V are very compatible and as expected the MAX-V is a bit faster as well for the similar devices.  Both family lines fit the design easily and is a little over 60% utilization but still well within the percentage for minor changes or additions for a new layout.  OK, since changes are going to be made, our engineering brain opens up the big gadget box and out pops the Engineering-Wish-List that was put aside during the initial development years back. Cool

MAX II   EPM1270T144C3  Quartus Rel  15.1

MAX V  5M1270ZT144C4  Quartus  Rel 15.1

  • Flow Status Successful - Sun Mar 07 07:45:43 2021
  • Quartus Prime Version  15.1.0 Build 185 10/21/2015 SJ Lite Edition
  • Revision Name   ADC_CHAN
  • Top-level Entity Name   ADC_CHAN
  • Family  MAX II
  • Device  EPM1270T144C3
  • Timing Models   Final
  • Total logic elements  842 / 1,270 ( 66 % )
  • Total pins  111 / 116 ( 96 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )
  • Flow Status Successful - Sun Mar 07 07:42:34 2021
  • Quartus Prime Version  15.1.0 Build 185 10/21/2015 SJ Lite Edition
  • Revision Name  ADC_CHAN
  • Top-level Entity Name  ADC_CHAN
  • Family  MAX V
  • Device  5M1270ZT144C4
  • Timing Models  Final
  • Total logic elements  842 / 1,270 ( 66 % )
  • Total pins  111 / 114 ( 97 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )

Table 22.0   Compilation of MAX-II vs MAX-V using  Quartus 15.1

We kept the same design that was compiled on release 15.1 created another new directory and copied the complete folder used in 15.1 to the new folder, opened the project with release 20.1 and did the conversion and ran the compiler.  Table 22.1 below shows the comparison from Release 15.1 and 20.1 compiled comparisons.  The red highlighted were the errors from the new 20.1 that stated the design would not fit in the selected device.  A group of 8 pins were added by the compiler for some reason as well as the extra 31%  of logic used for the same design.

MAX II  EPM1270T144C3  Quartus  Release  15.1

MAX II  EPM1270T144C3   Quartus  Release  20.1

  • Flow Status Successful - Sun Mar 07 07:45:43 2021
  • Quartus Prime Version   15.1.0 Build 185 10/21/2015 SJ Lite Edition
  • Revision Name   ADC_CHAN
  • Top-level Entity Name   ADC_CHAN
  • Family  MAX II
  • Device  EPM1270T144C3
  • Timing Models   Final
  • Total logic elements  842 / 1,270 ( 66 % )
  • Total pins  111 / 116 ( 96 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )
  • Flow Status Flow Failed - Sun Mar 07 07:11:54 2021
  • Quartus Prime Version   20.1.1 Build 720 11/11/2020 SJ Lite Edition
  • Revision Name   ADC_CHAN
  • Top-level Entity Name   ADC_CHAN
  • Family  MAX II
  • Device  EPM1270T144C3
  • Timing Models   Final
  • Total logic elements  1,227 / 1,270 ( 97 % )
  • Total pins  119 / 116 ( 103 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )

Table 22.1   Compilation of MAX-II=Quartus 15.1 vs MAX-II-Quartus 20.1

Running the same test on a MAX-II device selection the differences were not expected to be this far off.  Keep in mind that the memory requirements are 2GB RAM for the MAX series and un to 64GB for selected FPGA's required for release 20.1, our system is a quad 3.3GHz Intel processor with 16GB RAM Win10x64 Enterprise.  The test uses the same design file and ADC_CHAN.qsf setup file for all the tests, all the pin assignments were reset to allow the compiler to select the pins.

Here in the lab we have been running releases up to and including 15.1 on 8GB Windows 10x64 and 4GB on Windows XP for the Cyclone FPGA and MAX-II series devices for many years.  The lab systems now run 16GB on the Win 10x64 systems and the majority of software has been upgraded to run 64 bit.


Desktop Workstation Update
Update development desktop to dual core 4 logical processors with a total of 24GB memory since the minimum required for Quatrus 21.1 is 14GB this gives some flexibility. Also Release 21.1 requested the installation of Eclipse development system which was installed as prior to 21.1 installation.

OK, A new updated release for the Quartus Prime Web Edition has been released.  After Installing and running the same test I give Intel Corp a 5 star rating for addressing these issues and correcting them.  I also acknowledge the engineers at Intel for taking over the Programmable logic product line both Hardware and Software and all the hidden "Oh yea this tweak was there to make it work"   software patches.  For our small humble lab this is a great test since it allows the use of this product line for many generations to come.  

One has to think of the number of individuals employed at Intel Corp and the investment growth over the past several years along with some of the most challenging technical issues that have been addressed while maintaining a culture of innovation exemplifies strong leadership.

MAX II  EPM1270T144C3  Quartus  Release  15.1

MAX II  EPM1270T144C3   Quartus  Release  21.1

  • Flow Status Successful - Sun Mar 07 07:45:43 2021
  • Quartus Prime Version   15.1.0 Build 185 10/21/2015 SJ Lite Edition
  • Revision Name   ADC_CHAN
  • Top-level Entity Name   ADC_CHAN
  • Family  MAX II
  • Device  EPM1270T144C3
  • Timing Models   Final
  • Total logic elements  842 / 1,270 ( 66 % )
  • Total pins  111 / 116 ( 96 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )
  • Flow Status Successful - Thu Jan 27 09:41:22 2022
  • Quartus Prime Version   21.1.0 Build 842 10/21/2021 SJ Lite Edition
  • Revision Name   ADC_CHAN
  • Top-level Entity Name   ADC_CHAN
  • Family  MAX II
  • Device  EPM1270T144C3
  • Timing Models   Final
  • Total logic elements    842 / 1,270 ( 66 % )
  • Total pins  111 / 116 ( 96 % )
  • Total virtual pins  0
  • UFM blocks  1 / 1 ( 100 % )

Table 22.2   Compilation of MAX-II=Quartus 15.1 vs MAX-II-Quartus 21.1

BASIL Networks Review of the Development Supply Chain

---- Since the CPLD compilation proves out for updating to the latest Quartus Prime Lite removes the pressure to redirect the schedule timing to evaluate alternative FPGA/CPLD approaches for at least for the time being.  We will still review other FPGA and CPLD manufacturers along with the IDE software available at a lower priority.  Changing a major component line used in product development is challenging to say the least for any company or research lab.

There is an IDE limitation to the free web release of Quartus Prime Lite and that is the ability to run/create a Vector Wave Form (*.vwf) analysis, although the file is maintained when updating the database from an older release, the Quartus Prime Lite release 21.1  gives a license type error when attempting to open an updated project from a previous versions's design to 21.1 release and the create VHF file feature is not available in 21.1 Lit release.  This is a company's choice and right to select what a free release should provide.  The corporate difference between Intel; and Altera M&A, is Altera focused on selling silicon and gave the IDE software to develop a single chip application fully and added IP and high-end plug-in modules in the licensed release as well as the ability to interface multiple programmable logic devices.  Due to the several M&A's and the reorganization Intel decided not to give the same ability for the developer, however the Lite release is still very useful to develop a single chip application and the timing would have to depend on the designer and maybe a third party simulation application.  Or Intel could offer the VWF timing plug-in at a reduced price to allow the smaller developer to compete in the industry.

This being said there are only a few companies that manufacture FPGA's and CPLD and we will look at the remaining companies and review their product lines.   This means downloading the latest software and purchasing a few devices to test for functionality for our research definitely changes our direction as well as add a lot of time to the project.

------ One Typical Solution to the MaxII vs MaxV Interchangability ------
It would appear that a simple unique solution for the Max+Plus II and the Max V to be interchangeable would be to just take one of the power pins and use it for a LDO that would identify the power on the chip.  Since the I/O pins are already compatible over the 3.3 to 1.25 volt range the power pin would just have to sense the  supply voltage level.  This would allow a drop-in replacement from Max+Plus II to Max V directly and increase the usability of the product line and give an instant cost reduction as well.

Open Source vs Licensed vs Proprietary Software:
OK, why are we jumping into software now?  Well, it is always a good idea to look at what we want to do with the hardware, keeping in mind that some sort of software has to communicate with it, hence:  the 16 bit digital input and how the data is to be stored.  Since we are looking at a typical 10ns digital data collection on a BUS structure it would be a good idea to discuss some software to display this data logically.  OK, the old saying "when you have two or more lines of code there exists a troubleshooting requirement."  BASIL Networks over the years, accepted separate software contracts for other designers hardware only to come to a very fast realization that our quote of the day holds very true.  "People who are really serious about software should make their own hardware."  Alan  Curtis Kay ( May 17, 1940 )    So that is what we do, a full turnkey development, hardware software, documentation, training.  The decision was made very shortly after the company was started and our first big loss of what was supposed to be a simple software contract ended up being a redesign and coding that made it easy to update the company policy on only software contracts.  Hardware contracts work the same way when the outsource software company wants the hardware to be changed.

Software & Data Verification / Validation
One of the big issues today is with "software" used to setup and analyze data being collected,  Rewind! I meant over the years including today.  In the beginning even before the IBM-PC release in August 1981 there have been many software packages released to analyze research and test data collected.   This was accomplished by renting computer time all the way to purchasing "mini-computers" like DEC, Data General etc. to perform analysis to verify designs and research findings.  At that time it was very expensive to purchase complete hardware and software systems along with the analytical software compilers required to create analytical programs. BASIL Networks still has the licensed copies of Fortran, Pascal, C, BASIC that runs on MSDOS on the IBM-PC and compatibles, yes, 16 bit versions.   As the desktop PC evolved packages like MathCAD, MatLab, Maple and several others entered the PC Desktop market, however they were still expensive ranged from $1000 to as high as $5000 and were still 16 bit versions.  Here in the lab we purchased a couple of them only to realize the limitation along with the fact that supplemental software had to be written to meet the labs development needs.

The next issue we ran into in the lab was all the third party data collection hardware on the market have their own data file formats and to be fair they do offer some setup and display software that meets about 75% of the markets needs.  Our research lab is generally not part of that 75% and when you are researching new areas having limitation does not help to get accurate results required for proof of concept and design used for obtaining patents.  When presenting research data results, it is extremely important to be able to present the raw data, the equipment used along with all the parameters and setup on how the raw data was collected.  Presenting the final results through analytical algorithms is a great tool to allow the researcher to present how the data was manipulated, however this would all fall short if the raw data is not available to prove the findings.

What we realized over the years in the lab that it is not that difficult to develop analytical software with the easily available off-the-shelf math packages in C, Fortran and other languages, for the record, python language is not a math package software and was not designed to perform math gymnastics. It is however a very good process control package which may be linked to any external hardware for math gymnastics.  What makes this more attractive is that we are able to easily link it to our standard interface format for the display software already developed.  Yes, it does require you to learn software programming which is not very difficult.  Over the years we have used Assembly, BASIC, Fortran, Pascal and C with all the variations.  Assembly language is still used in the lab for driver development and interfacing to custom hardware as well as using some special interface IC's for specific bus types when needed.

16 Bit Logic Analyzer Display Controller Software:
So, here we are, what's next?  For our readers that have been following us over the past few years, we have decided to add some of our lab development software that has been and still is priceless during our development contracts.  Our main concern was how do we offer free software that is useful to the end user without adding the old paranoid feeling of  "if it is free you are the product" and what hidden stuff is in the application that sends info back to the manufacturer?  OK, lets address this issue now and put it to a rest.  BASIL Networks, PLLC software for this series follows under a separate BASIL Networks Blog Series End Users License Agreement (EULA).  This EULA will also be embedded in the Software IMAGE_Bitmap_16x16_ABOUT.jpg "About' page the application.  Oh, by the way - There are No PopUp Adds or any other annoying PopUp stuff,  Below is the Software EULA in a nutshell unless otherwise stated.  Our intent is to release an application that is useful to use for a long time, enjoy, grow and contribute.  It is always good to know the EULA before you open the box!

OK, So what was done to this software to extract it from the IBPD system Integrated Development Environment (IDE) ?  The modifications are listed below, in a nutshell which include all the links inside the IDE in order to make the application stand alone.  The entire system features are explained on the website that will save duplicate typing. The internal links common to all the other application packages within the IDE,,

OK, there is another limitation, or feature that has been removed for the free version and that is the encryption feature.  The encryption feature is part of the full IBPD systems Integrated Development Environment (IDE) that was developed over the years.  The encryption is a two fold methodology incorporating a stand alone standard 256 AES encryption (not part of the Win 10 AES internals)  as well as a proprietary Complex Obfuscating Methodology Block (COMB) to be discussed in a later series on encryption and security.  A quick list of the removed IDE features is as follows:

The hardware drivers and links were removed in order to make this a universal LAD controller that may be interfaced with existing digital data collection devices both old and new.  The external data interface is discussed following the main software in this part.  The LAD controller is a stand alone application that does not require any installation, just copy the files and directories in a top level directory and run the BPLAD.EXE file directly from the top level directory or create a desktop link to the top level directory that has the application.  The sub-directories are required to run this software and are referenced in the application to startup, save and organize the application.  You may also run this directly from a USB drive also as long as the subdirectories are on the USB drive.  One of the main features is the user has control of where the directories will be placed for each project and may load the directories for the current project at startup.  Not all the project features are incorporated into the stand alone application however, the directories may be manually setup for each project then loaded as required for the current project being worked on.

This is an extracted application from our internal IBPD (Interactive BUS Protocol Development) System that we use here in the lab that has been upgraded as required over the past 20 years to meet development requirements.  Yes, the original development started in 2000 as small separate applications where we soon realized that keeping track of software and projects with many applications has created confusion and time lost in the development process.  Hence: the IBPD (Interactive BUS Protocol Development) System was created and has evolved into a fully flexible innovative IDE.  This blog has opened the door for an opportunity to upgrade and pull out our "Engineers Wish List" for the next generation of challenges in the lab.  All the software presented here will run on Windows XP sp3 through and including Windows 10 x32/x64 without any special installation process, just copy to a top level directory and run, to remove it just delete the directory.  We will cover interfacing and other features after we present the dialogs and the ease of use.

To get a registered copy of this LAD controller software just click on the button below and fill out the registration form, a Link will be sent to validate the e-mail address.  You will receive a link to download the software registered to the information stated on the registration form.


The Logic Analyzer Display (LAD) controller is a full 16 bit display controller whose file structure contains all the necessary parameter information that is attached to the data file either RAW or converted from an external users data file to necessary levels being sampled.   The main purpose of the application is to allow the user to organize digital data collected with identification parameters that may be used to validate, troubleshoot and patent hardware that the data was collected on.  Figure 22.0 below shows the MAIN MENU for the LAD controller.

The Main Menu below shows 8 button group that the user may easily add links to any program that are simple convenient shortcuts that may link other programs that are used for the current project being worked on.  The buttons are configured through the Configure User Buttons on the main menu.  Command line links and commands are also allowed with these buttons and easily programmed.   Multiple configurations may be programmed and saved with the users project directory for each project.

A simple RTF editor used to read/write/edit RTF files that are linked to the data file to characterize and describe the data in the file for clarity and validation.  The data file RTF header allows a total of 65,000 bytes to be added to the data file when the data file is saved.   The project control has been disabled in the free release, however the user may create project directories and load them through the eight user buttons that will load the startup parameters from the saved project directory.

The explanation of the features for the LAD Database below  Trace colors and the Digital 16 bit word recognition pattern is maintained as well as the ability to have up to 256 different configurations of the data collected or imported to a standard file format.

LAD_MAIN_MENUFigure 22.0   ITF 16 Bit Logic Analyzer Display Controller   MAIN MENU

The purpose of the LAD database configuration is to keep all the parameters associated with the data collected  in one convenient place for each project.  All parameters are setup prior and are ready to be attached to the imported data file of the LAD Controller and saved to the SS_LAD sub directory setup from the users top level directory.  The user also has a 65000 character comment buffer that is through the RTF editor that is also attached to the data file and may be used for explaining any special features or configurations used during the collection of data.  A PDF file is also part of the project directories that is used to store any custom test fixture setup diagrams, processes and manuals used to collect data including any special components used.  This allows users to review data in years to come an get accurate information for reuse or verification processes.  Figure 22.2 below also shows the user may label each bit trace with a specific name, color, groups, assigned timing ID bars, Number of Samples, ands a 16 bit trigger pattern to identify the data being imported.   The Database files created from this dialog is saved in the default directory LAD_DBX shown in the directory structure in Figure 22.1 below.

The directory structure is a simple top level and sub-directory as shown in Figure 22.1 below.  The directory structure and the program startup files are small enough that duplication this structure for each project is simple and organized.  We have used this for many presentations and it is simple and effective and runs on a thumb drive.   There are three sub-directories off the Top Level BPLAD directory that are the Startup Directory SYS_LAD, the main application Help Directory LAD_HELP, and the project directories for the current project LAD_xxx.  Since the project and encryption features have been removed making this a stand alone application an duplicate for each project would be required.

Figure 22.1   ITF 16 Bit Logic Analyzer Display Controller  Directory Structure

The Configuration database allows the user to assign up to 256 unique configurations per Data File List block of data files an select any one for data importing.  The Data File List link that shows the number of different data imported files for the displayed configurations allow the user to maintain a common configuration setup for active projects and data collection.  The data file will incorporate the selected configuration to the imported data file and display the configuration when selected as shown in Figure 22.4 allowing easy organization and display of parameters used for the data collected displayed in the LAD graphic display of figure 22.3.

The user may have as many configuration databases required per project and these may also be sorted separately and placed in a project directory's data files for convenient loading / saving as desired.  The trigger pattern is a 16 bit pattern that consists of any combination of clock or level states will be displayed on the LAD graphic display shown in Figure 22..3

Figure 22.2   ITF 16 Bit Logic Analyzer Data File Header Software Setup

The explanation of the features for the LAD Display below  The update for this display now includes the ability to display trace data up to 16 Meg samples and sample rated as fast as 10 ns.  The graphic display shows the state of each bit and the hex 16 bit word.  There are many inexpensive logic analyzers on the market today to data at various sample rates and use the USB port to scan the data to the file system.  Some of the software is quite clever addressing the serial protocols directly at their adopted speeds.,  The ITF however is a straight forward parallel bit sample rate capture device that will sample data at 5ns for the full amount of SRAM installed and then display it at the actual fixed sample rate collected for the full memory.  Keep in mind that SRAM of the 10ns and faster is costly in some cases more than the device stating it can collect at 10ns for 256Meg words, just saying!

Figure 22.3   ITF 16 Bit Logic Analyzer Graphics Display

The complete file structure for this display is given in FileStructure_LAD.h  and is the same for the 16 channel Analog display controller as well which we will discuss in another part of this series.  The import file structure is also included in the header file in order to import any file data collected.  A free copy is available for the asking, all that is required is a valid e-mail address and registration,  a link will be e-mailed do download the registered software with all instructions.  Once the file is saved it will automatically setup the parameters that was saved with the file and automatically displayed when selected from the Data File List Dialog shown in Figure 22.4 below.

The data file organization for this applications allows the user to organize all the data files in a test sequence for the current project in a single Data File List for selective displaying graphically.  The files default to the BPLAD\SS_LAD\LAD_LAD directory,  however the user is free to save these in any file accessible to the system.  This allows the user to organize data files and document files per project in an organized directory structure for easy access.  The emphasis here is on the header files of each data file containing all the required information to identify the data collection, test setup and any special handling of the instrumentation used for the data being presented.

Figure 22.4   ITF 16 Bit Logic Analyzer Data File List Organization Display

ITF Peripheral & Software:
What a lesson learned about reuse that fits the presentation we gave a few parts back, this task was a challenge and for the better as well, since we did save some time in rewriting and creating all the dialogs.  In the process of removing the LAD application from the IBPD system and all the older drivers as well our initial presumed budget and time went completely in the deep six.  A lesson in reuse from the past, we did use about 35% of the code which included the dialogs, about what was expected from our past presentation on reuse.  To start the removal took much more time than just cutting and pasting since all the security features were tightly integrated and checked during several operations to prevent hacking.  Then there were the typical engineering wish list "like to add this" process of which actually happened, which then lead to a change in the ITF hardware design of course.  We will cover the hardware changes following this section.  Since this is a software application that requires the user to interface some external data file collected from third party hardware to import a data file an import function was also added for users to just click and import data from other data collection hardware.  So in the process of adding the import function the main body was updated also which when all put together added a lot more time and cost to the development process.  Again the TBD development surprises!

This application does not have any device drivers and will accept standard stream type data files as shown in figure 22.5 below.  For a simple update about data files, here in the lab we use the standard C, C++ or C# language file open [ FILE  *fopen(const char * filename, const char * mode ) ] commands to create a data file whenever possible, with embedded systems collecting data in a SD of FLASH memory we generally use Assembly for full control of the embedded system.  This stream type of  format just packs the data words one after another with no separation characters like CSV or any other delimiter.  It is very simple to open this file with a hex editor to get the offset of the first data word and put it in the HEX offset field of the LAD Import dialog to import the file in a single click.  Figure 22.5 below shows that the file offset is HEX 3C where the first 16 bit data is located.  The number of 16 bit data samples will be calculated at the end of the data import process and placed in the LAD Controller header file if the standard header format is not used and only the offset feature is used.  Logic Analyzer data files are usually a stream of data controlled by a fixed clock sample rate in order to monitor noise spikes or unwanted random data patterns so we only put the standard offset to remove the header of a data file, of course the parameters are setup in the database configuration prior to be able to keep a consolidated record of the collection.  As we move into the analog display side we will get to the other type of data file structures that have delimiters and multiple data values per row / column as the series moves forward.

Figure 22.5   ITF 16 Bit Logic Analyzer Data File Import Display

The other method of importing a data file is to create an intermediate file from your custom users data file which would require a small amount of programming.  There are so many different file formats for saving the data that it would be easier to just give a program that allows the user to just configure a data transfer program that addresses their file format.  The end result that is required to use the LAD Import File applications is given below.  With that in mind we have included the file structures for those that want to create their own transfer program to the preferred Import file format below.

typedef struct  _IMPORTDATAFILE
        int     DataSize;                  //- Data Number of Words (32bit value)
        U16 LaData[0x1000000];   //- Data Array [1-16Meg words] (16bit value)
  }IMPORTDATAFILE;              //- ImportLadFile   //- LADatFile structure ID

The import function for this release is very basic and may be used to bypass the header information and only transfer the data to also keep track of the original data file.   Figure 22.6 below is a typical display of a Hex Editor showing the first 16 bit data in this file starting at offset Hex 000003C which is the same file offset used in the dialog in Figure 22.5 above.

Figure 22.6   Hex Editor Shows A Raw Import Data Files HEX data

OK, there are many hex editors that are free and very useful, in this example we used UltraEdit from IDM a commercial release since we have been using this application for the past 20 years and it suites our need very well.  The free hex editor that we actually tested and sometimes use in the lab on test systems is NotePad++  with the Hex editor plugin for those that do not want to purchase a commercial version.  Keep in mind that BASIL Networks policy is not to endorse any products on this blog nor do we accept any monetary collaboration for products mentioned in this blog, this allows us to be completely unbiased and without conflict of interests, strictly scientific.

The software as we presented above is a general purpose display controller for a 16 bit data file of 2N points to be displayed as a Logic Analyzer Display (LAD) controller one bit at a time.  This LAD controller will handle serial protocols easily up to 10 ns clock rates for this free release and as fast as 1 ns for the commercial release device.  However, for this free application the LAD will handle protocols like  I2C, SPI, Microwire, Onewire,  Quad SPI and any 16 bit data collected easily.   

OK, what are the limitations?  The only limitation which is really not a serious limitation for this free application is the maximum data array size set at 16 Meg x16bit words which should be enough to handle any 16 bit Protocol in the embedded world.  If you were to price logic analyzers that handle 16 meg words x 16 bits or more at 10ns clock rates you will find the price tag anywhere from $50.00 to over $1000 depending on the software and hardware, keep in mind that stable periodic sampling at very fast rates are more difficult to maintain with DRAM that require refresh cycles than with true SRAM that do not required refresh.  Most of the inexpensive logic analyzers incorporate FPGA's and DRAM and lower the transfer rate as the number of channels increase also.  

Adding Features After The Fact Development:
The TBD syndrome effects:
OK, TBD's were addressed several times throughout this series so why now?  Well during the past year in the lab while using the IBPD software the old "Engineering What If " enters the picture since all the upgrades with the software and Engineers of course want a silver bullet that takes a very long time and lots of budget resources.  So, modifications of both the CPLD design as well as the software as mentioned above are on the table.  Needless to say this took some time and delayed the project again since a discussion on just what to add to update the package, so once again out came the engineering wish list, (TBD's at its best).  Once again it is easy to leave out requirements / want to have features even when you know what you are working on.  "Research is what I'm doing when I don't know what I'm doing"  - Wernher von Braun

The following features were added to the design of the digital interface and the analog interface.  These simple added features, of which the CPLD's are able to handle with ease which did cause a delay in the development as well as a redesign of the ITF, for the better though.Cool  To take something away from this blog this does present a fair experience on the "TBD syndrome."  In Data Acquisition some of these changes are not considered unreasonable additions however,  gaining experience on TBD popup delays during project development - priceless.

The addition of four A/D Channels:

The Digital I/O channel -

A brief comparison of the CPLD#1 A/D design and CPLD #2 High Speed Digital I/O Design.  Both incorporate a SRAM buffer to collect data at a periodic programmable rate or manually triggered externally.  Our engineering wish list discussed the possibility of a multi-core embedded ARM processor and a full DMA controller to be able to collect much larger block of data through a DMA (Direct Memory Access) method, however this was not an absolute requirement the pro's and con's did not balance out to incorporate this since the processors requirements for controlling other parts of the processes would delay the DMA cycle since RISC processors are not allowed to perform DMA in the middle of a majority of their instruction sets that involve memory transfers.  We will touch on this later.

However the design parameters are completely different, for one, the high speed digital I/O which requires a 10 ns static RAM or faster and the A/D Converter is much slower 1.0 us conversion time so a typical SRAM of 55ns is sufficient and much less costly.  A discussion of adding a double/triple/quad buffer SRAM to obtain a 1.0 ns (1 GHz) sample rate was discussed however it was decided not to add that type of high level change at this time as well it is not required for our current research projects in the lab.

The PCB design went from a single PCB to multiple PCB's which is OK, however the budget for PCB's just tripled to say the least.  The daughter boards for this design allows us to add CPLD's, embedded controllers and other logic as needed for various applications and for this design the daughter boards contains a duplicate CPLD and a higher speed memory (8ns) SRAM x18 bit where the 2 remaining bits are control bits for additional features we will be adding in the future.  High speed SRAM in the 8ns arena tend to be more costly since the demand is lower and applications are less, however for the Logic Analyzer they fit the application.

ITF PCB Layout:
OK, now for the ITF PCB shown in Figure 22.7 is the first prototype or Proof of Design (PoD) and may be used as a stand alone A/D with the interface to add a Logic Analyzer daughter board and an extended memory daughter board.  The 144 pin QFP CPLD and the TSOP memory are common since the memory is available in the same package to maintain chip replacement in-house.  Since this is not a ITAR design and is for educational purposes shopping around for the best PCB fab house is suggested and there are a lot of them globally.

The PCB below in Figure 22.7 is the actual ITF design, a 4 layer PCB with two trace layers and two power layers, 0.008" trace and space with the smallest plated through hole 0.015" to make manufacturing yield higher.  We also added a few more channels and made it a four channel 16 bit digital with a four channel analog with programmable gain for testing other analog and digital devices.  The design incorporates a USB 3.0, 2.0 interface on the first board to make it a full stand alone board, however the next revision will be not have this and will be using a separate embedded processor at the top level to address all types of network interfaces and daughter boards independently.  The TSOP-I SRAM will interchange high speed SRAM up to 4 Meg x 16 bits per chip per channel for the analog inputs.  The 144 pin CPLD is a MAX-II  EPM1270T144C5 is available from several suppliers and is in full production.  The four 26 pin headers are for a daughter board that hold additional circuitry for the digital I/O and connectors as well as for future use as required.  At this time it is just a 16 bit digital I/O and the daughter board will incorporate the digital buffer IC's.  We will be assembling this board in the lab since it has no BGA components and can easily be hand soldered, one of the main requirements for smaller companies in-house test equipment.

Figure 22.7   ITF PCB  4 Channel 16 Bit Digital And Analog Input

A/D Channel vs Data I/O Throughput 
A quick comparison of the two technologies, the A/D Channel is a 1.0 us Sample rate via a 50MHz 16 bit  (20ns x16) SPI type serial interface.  The actual A/D conversion time is approximately 700ns which allows ample time for the serial data to be transferred and put in the SRAM on board without missing any bits or points until the number of samples has been obtained.  Another A/D we looked at is the MAX11198ATE+T is a dual 2Msps A/D one clock with dual data serial out, the thought was a simple separate Analog trigger independent of the data collection and may be used for monitoring as well, this is on the Engineering Wish List at this time.  This design however, does not have the dual 2Msaps dual A/D converter design it incorporates the AD7980 Single channel A/D chip.

The Parallel 16 bit interface in CPLD #2 used for the Logic Analyzer is different since we require the full (10ns) 100 MHz x16 bit transfer rate without missing bits.  So if you want a true 10ns sample rate you have to lock the data sample within 5ns which is OK for the CPLD we are using, however the memory access should be less than 10ns to be safe, say 5ns to 8ns SRAM would be better.  This simply states that the full time cycle to write to memory is less than 10ns in order to meet the 100 MHz transfer rate.  The faster the SRAM the higher the cost also there are a smaller selection to choose from when designing with 10ns or faster SRAM devices.  There is a list below of the selected high speed SRAM devices that are available for this project at this time.  Also you can search on Octopart and others like SnapEDA and several distributors for these parts is a good place to start.  For a quick reference a 450ps (0.45 ns) SRAM 4Megx16 is only around $130 plus per IC in a 165-ball FBGA.

Peripheral vs. Functions
When designing any product including test fixtures the Peripheral vs Function discussion will always arise to insure the best price per performance is addressed and not impossible to achieve.  With the technology advancing at such a rapid rate ICs are being release on a regular basis to eliminate support ICs as well as reduce design and testing time.  There are pros and cons with all designs and they have to be addressed.  The approach we are applying in the development of the ITF is flexibility, programmability and separating the front end sensing to separate IC(s).  Of course since this is a test fixture and we are modifying the original design the "Engineering Wish List", will always surface -hint- we request the input of a business managers sense of influence to insure we do not fall over the cliff in time and budget.Cool

How to Obtain the LAD Software and a Finished ITF:
To get a registered copy of this software click on the button below, Fill in the form, a Link will be sent to validate the e-mail address along with a link to download the software.  


Our plans when the ITF is finished, is to offer an ITF to the public with many more features than the one being developed for this presentation, however that is still on the table.  We already completed two different PoD products to get ready for manufacturing and offering custom development for contract manufacturing companies / entrepreneur small company that want to setup a development test base for future and present development contracts.  Please use the BASIL Networks Contact Form to be put on a mailing list when we are ready to supply the manufacturing prints if you are interested in purchasing the entire system manufactured and tested.  The instrumentation developed in our lab is specific to the needs of the current research projects being studied and not necessarily a full drawn out market research for competing in the market, however there are times when the instrumentation really fits a market niche.


So, this has been an interesting part for the IoT Core platform Development.  The experience of having the selected components discontinued in the middle of a design is real and over the 40 years that BASIL Networks was active this only happened 4 times all with Intel rolling over silicon and letting everyone know that last minute with a short time to do a lifetime buy which we will not do here.  We are actively looking at other companies to form a collaboration with to help prevent this from happening again.   CPLD's and FPGA's are here to stay as well as the embedded processors so we should look at other ways to collaborate to compete in the industry.

We see how easy the "TBD" acronym gets out of control and just seems to tangent into its own entity of development and seems to manipulate all aspects of the design.  BASIL Networks has been in business over 40 years and we have very slowly learned the hard way not to just put TBD's into a contract without specific expectations and discussion on how these would effect the overall performance.  If the performance interaction is un clear then the contract must be kept open for discussion for that area an performance and price must be allow to be negotiated to cover the expense.   Yes, This sounds like a bad leverage for competition, however, it can be much more costly when you are paying for a development when you should be getting paid for it.   Yes, there are competitive companies that will make statements that they will do that for a fixed price even though you know that it cannot be done for that price!  It is up to you to not only maintain your integrity but also to instruct the customer to bring their knowledge level to a higher understanding.   Remember it is ok to break even once in a while but to maintain a business and protect employees you must maintain a profit.

Since it has been a while since our last presentation, a catchup and a short sidestep from the design would be good to get back to the swing of things;  this series will continue with the IoT Platform design and the ITF design.  After presenting the Logic Analyzer Display controller we thought it would be a good learning tool to give out the software that will be used with the ITF.  The LAD controller is flexible to display any digital bit display that is useful in checking a number of serial data protocols or word data collected in a file.

One issue that has to be addressed is the actual timing diagram after the timing analysis process is completed.  A simulated timing diagram of the Quartus Prime Lite gives a license not valid for process error.  Third party software may be purchased or a full subscription license from Intel will work as well. for now since the Max+Plus II is back on the availability list an older release of Quatrus will work fine.  We are still going to look at the MAX-10 FPGA device for future development as well snow that confidence is restored in the development software.

Updating and Modifying CPLDs / FPGAs
Here in the lab we have been very fortunate until just recently that our internally designed and developed test fixtures have stood the test of time for 15 plus year.  We have now updating all our test fixtures, basically redesigning them due to discontinued components and data collection software to run on Windows 10x64 Enterprise.  We still program using win32 for some of the more common applications and in the process of testing out programming with win64 which is an interesting and challenging endeavor to say the least.  For our older ISA Bus peripherals, obtaining a motherboard with PCI and ISA slots that are compatible with older boards and run Windows 10 Enterprise x64 presents a small challenge but are still available.  The best approach is still to design the test fixtures to meet our needs with components that are anticipated to be around several years.  Since Intel has acquired Altera several devices have been discontinued, however the ones we have picked have been discontinued a few months ago.  Also the software has several changes due to licensing transfers during the acquisition that we are still dealing with.  This discontinued product list has caused a setback in timing as well as a budget over run and will take some time to recover.  These are the Oops of a TBD and of course the M&A syndrome.

CPLD Register Identification
Since we neglected this because of the Re-use factor the thought was since all the matrix was already defined prior all that would have to be done is reassigning the bits for each register.  Well that did not turn out as expected and it very seldom does, that lead to the re-mapping of the register set as well.  The redesign became obvious when we started modifying the design realizing that it was over 50% change.  At that point purely by experience it was decided to just start from scratch and layout the CPLD to fit the application with a few spare I/O pins for future growth.  In this reuse case it was fortunate that the redesign was recognized early before many man hours of troubleshooting and development were lost.

Being that the Max+Plus II is now back on the availability list, we will finish our development using the Max line.
It would appear that a simple unique solution for the Max+Plus II and the Max V to be inter-changeable would be to just take one of the power pins and use it for a LDO regulator that would identify the power on the chip.  Since the I/O pins are already compatible over the 3.3 to 1.25 volt range, the power pin would just have to sense the  supply voltage level.  This would allow a drop-in replacement from Max+Plus II to Max V directly and increase the usability of the product line and give an instant cost reduction as well

If we are to use the latest release 20.1 of the software we will have to seriously look at the design and determine if we should use the new MAX-10 FPGA along with the cost and time impact.  CPLD's and FPGA's are very competitive in the marketplace today and if you decide to switch manufacturers the learning curve may be steeper that expected.  Until the root cause of the increase in pin assignments and the increase in logic elements used in the latest release is understood, we will use release 15.1  for the Proof of Design (PoD) at this time.

Final Note
Since repetitiveness is the mother of retention, "Changing poor engineering habits are difficult however not impossible to correct".   Humans are very flexible they all have the ability of learning anything with applied effort, the only impasse is the mind set that if negative will defeat any attempt to grow and instill fear of learning.  The key is to acknowledge the initial behavior, no, it will not change overnight - it took a while to become rooted.  "TBD is a typical behavior when the desire to obtain a contract exceeds the common sense."

Bringing the development behavior to the surface and acknowledging the behavior is the first step in this series to bring the development process to a winning level.   The expectations of this and other series on the blog is to encourage the self behavioral changes as well as present a project that is useful for many applications.  Behavioral modifications is a personal and private process that takes time which requires trust within ones self.

As the series progresses the author, Sal Tuzzo will be available for discussion through the BASIL Networks Contact Form for those that want to apply this series to conduct their own experiments.  I will always be appreciative for the private comments sent through the contact form for suggestions and advice during the development of this series.  This is a growing opportunity for everyone entering into product development as well as a great review for us "well seasoned" in the field.

It is recommended for those that have specific questions to use the BASIL Networks Contact Form for questions to separate them from getting lost in the general comments for each blog presentation.  For all specific design request or contracts please feel free to contact me.

Reference Links:

ITF Selected Components

MAX-II EPM1270T144C5  Pin Assignment Template

BOM Spreadsheet and Component datasheets ZIP file

PGA281 Programmable gain Amplifier Datasheet
IS66WVE4M16EBLL 64Mbit (4M x16) Pseudo SRAM Datasheet
Alliance Memory AS1C8M16PL 128Mbit (8Meg x16) Pseudo SRAM

FileStructure_LAD.h  - File structure for LAD Controller Software

Altera® Quartus Download 9.1 sp2 from Archives
Intel®/Altera® Quartus Lite xx.x Download

Requirements Traceability Matrix  (RTM)
Project Management
Mezzanine Board

The majority of Internet scheme and protocol information are from a few open public information sources on the net, IETF (Internet Engineering Task Force) RFC's that explain details on the application of the protocols used for both IPv4 and IPv6 as well as experimental protocols for the next generation Internet and the Network Sorcery web site.  The remaining of this series on the IoT platform will be from BASIL Networks MDM (Modular Design Methodology) applied with the Socratic teaching method.   Thank You - expand your horizon- Sal Tuzzo

Network Sorcery:
The Internet Engineering task Force: IETF - RFC references

Memory Segmentation
The Memory Management Unit (MMU)
Virtual Address Space
Virtual Addresses and Page Tables
Extended Memory

Previous Part 21 IoT Core Platform - Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Mar  23rd, 2020)


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Sal (JT) Tuzzo - Founder CEO/CTO BASIL Networks, PLLC.
Sal may be contacted directly through this sites Contact Form or
through LinkedIn

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