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Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-19 | BASIL Networks Blog BN'B

17 Jun, 2019

Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-19

Part 19: IoT Core Platform Development;- Peripheral I/O Device Design
The IoT Embedded Core Platform -Peripheral Devices Real World Testing - Continued

"If you keep on doing what you've always done, you will keep on getting what you've always gotten" Traced to Henry Ford (July 30, 1863-Apr 7, 1947) and Tony Robbins (Feb 29, 1960 - age 59)

There have been many paraphrases of this much used quote - the one that stand out along side of it is "Insanity is doing the same thing over and over again and expecting different results" You would probably say to yourself that is an Albert Einstein quote, and you would probably be close to right since there have been no known documents by Albert Einstein containing this quote.  However, it was researched and "vetted" by Michael Becker an editor at the Bozeman Daily Chronicle.  The earliest written form was found in- Rita Mae Brown  (Nov 28, 1944 -Age 74) Quote from 1983 fictional book "Sudden Death" character Jane Fulton  In fact this and similar quotes are referenced in so many places, show that misattribution like these happen often.

OK, what is the point here?
Many years experience in product design and troubleshooter in several fields of interest these above misquoted phrases seams to always appear before and during outside help is brought in.  OK, here we go making a broad statement, All, yes, "All" companies at one time or another face a situation that in-house talent cannot solve the issues at hand, or to put it another way, the current in-house talented resources are not recognized within the organizations culture.  On many occasions when called to troubleshoot or assist with an issue that a client is having difficulty in solving, these or very similar quotes seem to always pop up, "This is how we always do it! or "managements process guideline require we follow these parameters", and so, on and on.

As we stated in past presentations in this series development costs are easily exceeded when the performance expectations and in that case performance requirements are not documented properly or the infamous "TBD".  This forces a direction change "AND" direction changes are commonly not listed as part of  performance expectations.  Sometimes the development "process" is faulty or just plain broken period.  The intent of this series in not to maintain the insanity of over budget development costs but to disrupt it in order to allow the creation of new habits that will give a solid foundation for engineering practices to be successful when starting a development project.

IoT-Index Quick Links

Quick review to set the atmosphere for Part 19:
A lot of information was covered over the past 18 presentations of this series.  The progression from presenting an important explanation of safety, security and privacy of data, Internet basics from real basic to protocol complexities, conceptualizing a project development, presenting the need for secure accurate documentation as well storing that documentation where it is accessible during and after the product development cycle and of course the need to design in security and privacy during the conceptual development of a project.  

For review, the current Core Platform IoT development main focus is two fold, first an educational project development for the entrepreneurial mindset and the project applications of remote sensing and control incorporating safety, security and privacy over a wide range of peripherals including wireless.  This should be kept in mind since we will be designing in some redundancy for reliability and security.

The ITF development Project:
As we see this is a project within itself to show product development direction and expectations easily shows how resources are weighted and required for both product development, engineering performance testing and production.  The ADC-CHAN interface was selected since it was a "reuse" design and how it is to be modified to fit our application which would represent the standard peripheral interface to the IoT Core Platform CPU peripheral BUS requirements.  Initially presenting part of the Interface Test Fixture (ITF) to handle the remaining peripheral development for the series and continuing on with completing the  Interface Test Fixture (ITF) then go back to completing the ADC-CHAN Analog input design to insure the interface performance expectations.

The ITF did create a change in direction, however did not change the desired results, this is not only common in development projects but is some cases required to meet the desired expectations.  The issues here are handling multiple projects, resources available and the changed timeline, just a short change in direction to complete the objective.  A validation that the real time product development process is far from being a linear process from conception to finished product.  

Over the past 40 plus years of being involved with product design, research, investigations and management so much has changed incorporating more tools to make manufacturing more controlled, design and development more accessible to all levels while increasing the level of knowledge for society adding more responsibility and accountability and freedom of innovation for individuals to take action and bring their ideas to fruition.


What we want to cover in Part 19:
In Part-16,17,and 18 we addressed the issue of why we should consider testing of the peripherals (Proof of Design) PoD with a prototype build to insure when we interconnect several of the peripherals the throughput required for the applications will be met.  This allows the opportunity to change the development direction from the peripheral point of view if performance expectations become an issue. Developing a test methodology that will be used for testing peripherals for the platform keeping in mind peripheral throughput limitations. These are new habits being developed at a conscience mind set level that will connect to become the default critical thought process during development.  With that stated we will continue moving forward with detailing the Interface Test Fixture (ITF).

The design process in this part includes:

Updating the IPD project documentation for the ITF (Interface Test Fixture) to keep track of the development process, "Documentation is a living process during development", a good habit to make!  The reference for the ITF is the functional block diagram Figure 16.1

OK, some information on re-use - With the ADC-CHAN design the reason it was easily presented was because it was a "Re-use" design so all the preliminary design work was completed.  Yes, this was selected with expectations to present the re-use with modifications vs the full design from scratch.  The full design process will be presented for CPLD#2 specifically from scratch to see what is involved with creating the design from start to finish and to review the reuse debate syndrome.  

Some questions answered from our readers

Lets Get Started:

Some questions answered from our readers
I received a very good request from a reader.  "Why not link all the references to the original part throughout the series calling up the specific part  for review when referenced.?"  Well the answer for me is simple - that would require a lot of maintenance and the probability of broken links are way too great.  The other issue is that each of the blogs are referenced from a database and references would have to load the entire blog to display. It is easier and efficient to just create a new link for the part in question than to jump back into a previous part where some browsers may or may not open it in a new page or tab.  This will help the reader to focus on the current task at hand with less diversion.

Another question is why five different JTAG isolation channels?  This initial design is for assembly houses that will address many different types of programmable devices.  For those that only work on one type of programmable logic a single channel; is fine and if another type is required an simple changing of the JTAG wires will accommodate various types of programmers.  Here in the lab we have a separate desktop PC that is used primarily for CPLD and FPGA programming connected to the development network.  This is easily maintained since the logic manufacturers provide separate stand alone programmers.

From our experiences connecting and reconnecting and of course the occasional oops did not want that to happen, it is easier and cost effected to separate these functions for manufacturer of the CPLD's and other programmable logic.  We will add a single channel JTAG isolation channel for those that only need a single channel.  Remember this is an educational series and you have the ability to add value to any design that you decide to undertake. This series will walk you through step by step of product development..

Remember changing direction overnight does not mean changing goals our the final destination, it is just a better way to insure you will reach the desired destination.  In my years of exposure to the design arena as a designer,troubleshooter and mentor I have had the honor of experiencing innovative and passionate creators to realize that the creative thought process of an individual is not a linear step function, 1, 2, 3 ...N, probably because humans are not robots, that follow a preprogrammed set of processes as some may think of engineers.  The innovation of the human mind subconsciously is always performing scenarios to find the best solution for the task at hand and "developing habits along the way".

OK another change of direction that we are considering- we have a complete video creation system here in the lab that we have been encouraged to use for this series.  We have created videos for client business presentations but have not created on to put on-line, so we are discussing putting this series in video format that will have much more content and technology sharing along with encouragement and stories from other entrepreneurs and how they handled different situations.   For those interested please contact us using the BASIL Networks Contact Form for more information on when this will be available.

OK, a quick review of the documentation system we will be using, Yes again, Ok I'm sounding like management now, "are we there yet?" - so what does that all mean to this series?  This means that to assist this innovative development process that may change direction at times from one development task to another a tracking system should meet the following requirements.

  1. Interactive - by second nature without thought
  2. Flexibility - being able to record changes and additions in real time.  During development changes in one project can easily effect another project.
  3. Multiple Project Tracking - This is where we are now - being able to start and track new projects that will eventually interact with the product development at hand, hence: the IoT Core Platform development project.
    So, the ITF Project name given is- Universal_Peripheral_ITF previously
    AND-- We are going to make some more changes, again---

Repetition is the mother of retention,  wait a minute!..., I think I read that somewhere before in a different colorCool


The ITF BUS interface Block Diagram:
We will be designing the I/O peripheral BUS architecture interface in this part as shown in Figure 17.2 Functional Block Diagram of the ITF Data I/O Section which is a redesign from several years ago when 208 pin MAX CPLDs were available from Altera® and have been discontinued and no longer available.  We could possibly get these 208 pin CPLD's on the surplus market however it is not recommended since they will not be readily available in time. Since we address and emphasize longevity for this design the components should be up to date and not on any Not-Recommended-For-New-Designs list.  The 144 pin is readily available and up to date for this so we will design using two of them to perform the required functions for the ITF.  As stated before we use the TQFP package since they can be easily installed and removed manually if repairs are required.

There are a few ways to approach a CPLD design from scratch two of the more common ways are explained below along with the approach this series will use.;

Just build the logic block diagram with everything you want on it then try and compile the design.  This will generally tell you if there are enough pins available for the design.  From there just start putting blocks of the design on another CPLD and shuffle the blocks until you get the results desired.  This method forces the designer to address sections of the I/O in blocks that are manageable with the understanding they will be moved around.  This will develop a solid sense of Modular Design Methodology (MDM) and by the nature of the habit will allow you to move design blocks to fit the application.  This approach does take a few years prior experience in designing I/O.  BASIL Networks does have a library of designs and part of this design will be incorporated into the ITF.  

A more systematic approach is to identify all the pin assignments first then design each section around the pin assignments.  This approach is a bit more structured which by the way still requires a single designer and not meant to be split to several designers.  Since this is an educational series we will take the more difficult structured approach and incorporate it into the IPD System to develop good engineering habits.  The previous way does not allow for detailed documentation on the ITF and is generally created after the design.  Humor - there are some that think this is possible and expect a working device as well.

Since we are using multiple devices the challenge becomes how do we separate the functions for everything to fit and insure the performance.  We have separated the ITF functions in Part 17 and we will take each section and obtain a pin requirement for each. Figure 19.1 shows the entire CPLD Block Interaction.

Figure 19.1   Functional CPLD Interface Block Diagram of the ITF

Peripheral I/O BUS to CPLD#2 Data Transfer:

This CPLD is assigned the task of communicating with the several attached Parallel I/O devices and passing the data to CPLD #2   As we design this CPLD we will probably expect to add a few functions along the way as most designers do to make testing easier.  This isolation is more cumbersome than difficult part of the design since it entails a set of digital isolators.  Since the Isolation is separate from the CPLD we will design the CPLD first then the Isolation section.  The pin assignments will he assigned after the Isolation interface is designed to simplify the layout of the design.

CPLD#2 Memory Data and Real World Interface:
Transferring Peripheral Data From CPLD#1 To Desktop

This CPLD is assigned the task of collecting the data from CPLD#1 and communications with the desktop for analysis.  This is shown in Figures 17.4 the On-Board Memory Buffer and Figure 17.5 USB Interconnect BUS.  

It appears that both CPLDs have a few pins to spare while maintaining CPLD to CPLD communications and control for the remaining serial I/O functions like SPI and I2C control.  To start we will create a functional block diagram of each CPLD and the functions they have to perform to communicate with the controlling desktop.  For this design we will look at a simple USB 2.0 interface as we discussed in previous parts of the series.  If a high level of security is required for all test equipment we have security level test interfaces that will comply to compartmental security standards.  We will separate the functions as we create the documentation for each CPLD.

CPLD-2 Functional Block Diagram:
Starting with CPLD#2 mainly because it is the CPLD that will not be reprogrammed or extra functions added once designed.  This is due to the fact that changing high speed  CPLD/FPGA design changes propagation delays and may render the device non functional after compilation, A risk that many development managers take and find that the cost exceeds the expectations exponentially.

CPLD-2 is the main CPLD for the ITF because it incorporates a high speed I/O memory buffer for testing performance of peripherals.  The features of this I/O memory buffer has to be fully programmable to transfer data at a selected transfer rate to test performance limits of attached peripherals.  To handle this we will incorporate a fixed TCXO along with a programmable DDS chip to control the actual transfer rate.  The use of the DDS allows us to add programmable phase shift to the synchronous edge of the reference frequency in order to test performance.  This changes the ITF CPLD#2 functional block diagram to add the DDS Timing Control.  Figure 19.2 shows the new functional block diagram for CPLD#2.  As shown the design changes as the development continues and the documentation of the process is required to handle these unexpected changes.

This is the CPLD that will remain fixed and not re-programmed to add other functionality.  CPLD#1 is the general interface CPLD and will have the flexibility to add functions as needed.  This is the leverage of adding a second CPLD to the test fixture gives for future enhancements without redesigning the entire fixture.

Oops - there are still free cells and the design worked before we added this small change - just a few gates and a small register.  Many of us in the FPGA/CPLD design field realize that when you start adding features to FPGAs/CPLDs many strange things start to happen, like the propagation delays change and registers seem to be missing bits at certain bit weighting, these are the pitfalls that few talk about and many are misinformed of the consequences of just adding another couple of bit control to a working design.  These phenomenon have been observed in the lab during development many times and at time manual tracing of the FPGA design has to be performed patiently to fix the problem.  It would be more cost effective to just keep a working fixed design in a CPLD/FPGA and adding a second CPLD/.FPGA for the expansion of features that may be required later.

Figure 19.2  CPLD #2 Functional Diagram I/O Assignment Blocks

OK, to start the development process for CPLD#2 we would list the functions that this CPLD is required to perform.  Since this CPLD requires a couple of external components, high speed RAM a USB interface for the real world.  If we require full security in communicating with the ITF we would use a RJ45 network connection with another embedded processor with encryption for this.  Oh wait - that is one of the applications for this IoT Core Platform alt.  Characterization of these components are required to insure the CPLD is interfaced to give the expected performance and of course a timing analysis to see if the speeds and interface requirements match the CPLD's I/O characteristics.

CPLD#2 Proposed Timing Diagram similar to the one we created for the AD_CHAN peripheral except this one will have to work at 20ns throughputs.  The expectation of this memory buffer is to allow peripherals attached to be able to transfer peripheral data to the memory buffer without CPU intervention.  This is essentially a Direct Memory Access (DMA) controller for any peripheral connected.  In our embedded IoT Peripheral platform was defined back in Figure 12.3 IoT Platform Interface Function Segment Mapping That shows a DMA controller interface to memory.  This interface is very high speed and may be added to the IoT Platform as well if the application requires multiple peripheral and multiple high speed buffers.

The ITF Direct Memory Access Controller:
In some Embedded Processors the a DMA controller is already implemented and only allow DMA transfers to selected peripherals that are embedded on the chip however, having total control to select the peripherals gives far more flexibility through a separate DMA controller.  This DMA implementation on the ITF is a good exercise to understand the creation of timing diagrams before jumping into the fun stuff designing logic circuits On-The-Fly. The DMA sequence of operations has two sections, the setup and the data transfer on request.

Sequence Setup for CPLD Memory Buffer Controller

On DMA Request

The Art of Timing Diagram Creation:
There are many approaches to designing digital system, the approach here is to develop a timing diagram of the critical data paths used in the CPLD that include the DMA control data transfer from the Data Bus and a control interface for the real world data transfers.  Lets design this timing diagram from scratch to understand the process of developing a timing diagram since we just presented a timing diagram in the AD-CHAN peripheral without showing the actual mindset and process to develop it.

Some basic logic skills are required to visualize the sequence data flow while creating the timing diagram.  For those beginning in the field this process becomes second nature with digital design experience is acquired and being exposed to system integration techniques of peripherals and devices, it just takes some practice and a little bit of imagination.

The ITF memory buffer is essentially a Direct Memory Access (DMA) controller, so to start lets look at a single channel DMA controller for now.  From the Sequence Setup for CPLD Memory Buffer Controller above we see the setup registers that are required.  

Required Data Transfer Features:

From the above sentence we deduce that some type of end count register/counter has to be implemented to keep track of the number of transfers in order to maintain a specified SAR and memory block to control data transfers.  We will call this the Terminal Count Register (TCR), also some type of a latch to be set when the TCR ends its count.  A current Status Register would be good to monitor the state of the transfers without disrupting the transfer, so a Current Status Register (CSR).  The Status Register is a bit oriented register made up of one bit registers that are controlled (Set/Reset) individually to identify the current status of the device.  

OK, Lets Group The Given Registers:

How Much Static RAM to design in?  The High Speed Static RAM selected has asynchronous read/write times of 10ns and 20ns. The selection here is the 2 Meg x16 10ns chip IS61WV204816BLL-10TLI and is readily available.  If we want to add up to four of these chips for a total of eight Meg x 16 bits the MAD and the SAR have to be wide enough to handle the memory.  For an eight Meg address we would require a 23 bit register for the MAR, SAR and the TCR.  If we wanted more than one channel we would have to repeat this set for each channel, so as we see this can easily use up CPLD resources so we will keep it at a single channel at this time.

Now imagine the data flow process and what sequence of synchronized pulses have to happen for each data transfer.  We also have to be able to setup the DMA controller prior to any data transfers to insure the data will be placed in memory where directed.  The next section is how the data transfers are actually performed at high speed what digital lines have to be used to perform the operation successfully.  This is where the control, pulse, strobe and status lines of the timing diagram are transcribed on the timing diagram.  

In order to insure all memory data transfers a top level clock is used to synchronize the data transfer and should be at least 2x faster than the memory R/W time.   That leaves us with 10ns=100MHz for the memory and 5ns=200MHz clock frequency to latch the data for transfer.  

Creating a Timing Diagram:
OK - as a rule for the lab during development all timing diagrams are drawn on a B-Size (11x17 landscape) format.  This has been found to be the best fit for these typed of developments.  The Lab software for this is Visio and has been implemented several years before Microsoft acquired Visio Corporation in Jan 2000.  The best part of this is all the old drawing using Visio 5.0 before the acquisition work fine so the transition was seamless.

Some CPLD register characteristics - in the lab it has been tested that a 4ns device has the capability of loading a register in less than 10ns so as a default to start the design and create timing diagrams 10ns is a fair place to start.  When you compile and assign pins to the CPLD the IDE will perform a timing analysis to show the actual load requirements.  The propagation delays for wired vertical meshes adds about 1.5ns per connection so we added at least 15ns between load pulses in order to avoid data bus and general trace routing.  The time between load pulses depends on the embedded processor selected and the nesting level to the actual I/O device that controls the setup sequence.  Since this is from a USB bridge the time is generally quite long in comparison these times are for sequence of operation only.

CPLD#2 Setup Timing Diagram:
Starting off simple to understand the mindset of developing timing diagrams, all technology that contains a process flow will have a time line and a flow diagram to represent it.  "The initial mindset of innovation is to be able to understand what drives the flow of a process."

The first part the CPLD#2 design is to create a hardware flow diagram of what functions exists to obtain the expected performance.  Figure 19.3 shows the hardware data flow diagram  for CPLD#2  DMA function.

Figure 19.3  CPLD #2 Register Setup Flow Process Timing Diagram #1 Section

Figure 19.4 shows the timing diagram created from hardware flow diagram in 19.3.  This process is an industrial preferred design process, however there are many companies and engineers that just jump into a design and brute force there way until they get something that sort of works.  Granted this is a more time consuming process however, many of the performance expectation are more clear using this method as well as allowing a team approach to allow changes.

Figure 19.4  CPLD #2 Register Setup Timing Diagram #1 Section

The timing diagram in Figure 19.3 above is a separate part of the CPLD design which are the setup registers for the DMA controller.  The 200MHz clock is not part of the setup sequence it is only there as a reference starting point. The Data IO BUS is the real world BUS from the USB bridge to the CPLD and is the main connection bridge to the desktop or laptop that is being used to control the ITF.

Creating the Memory Data Transfer Timing:
OK, reviewing the Required Data Transfer Features: above we will start to create a sequence or a data path for the timing diagram.  The end results are the capability to transfer data to/from memory directly without any processor intervention other than the initial setup, simple.  The Clock Timing IC has to have the capability of generating 10ns pulses.  The initial thought was to use a simple counter with a 200MHz clock input that will count down and put a Terminal Count pulse when it is at zero, however that would only give us a divide by 2n and as "n" increases the delta between steps increases and fine tuning the performance is not possible.  The solution is to change the design a bit and add a DDS IC which allows programmable 32 bit frequency tuning and 14 bit programmable phase control to measure performance accurately.  The DDS IC that will handle all the frequency requirements is Analog Devices® AD9954 a 400 MSPS 14bit DDS capable of 32 bit frequency tuning and 14 bit programmable phase offset.  This will handle all the current and future requirements for Digital I/O that we would encounter for this generation.  Also this would require a stable frequency reference source which is the Analog Devices®  AD9540 a 655 MHz Low Jitter Clock Generator that is tuned for 400 MHz clock for the DDS that has a 48 bit frequency tuning word resolution and a 14 bit programmable phase offset.  This chip does require an additional 8 pins for all the features, 4 for the serial communications and three bits for up to eight separate clock profiles.  Both chips use a SPI interface communications only consumes a few pins and is controlled through the USB interface directly which is also supported by the IBPD System which makes it easy to setup.  As we see Designs just seem to grow from the initial idea or concept as the details are presented, flexibility is mandatory in order to obtain the performance required from the ITF.  

The Status & Control Register (CSR)
The CSR allows the user to Arm, Set Direction, Terminate Scan, Manually Start Scan and other functions that will be defined as we create the timing diagram.  The CSR is the last register to access to arm the DMA controller and the first to end the scan as a starting point.  The actual bits could be assigned at this point to aid in the timing diagram.  The table below is a typical eight bit status register assignments for this type of device.  The remaining bits assignments will be added as the design continues.

Write [W
7 BUSY R/W [R]  - 0 = Disarmed Off,  1 - BUSY - DMA Armed
[W] - 0 = Clear-Disarm DMA,  1 = Arm DMA for transfer On
6     TBD
5     TBD
4 DIR R/W 0 = Data Transfer From Memory To  Device
1 = Data Transfer From Device To Memory
3     TBD
2 Ref Profile

Status Register Control Group for DDS Reference Clock
2  1  0 Bits
1  1  1   = Reference Clock Profile 7
1  1  0   = Reference Clock Profile 6
1  0  1   = Reference Clock Profile 5
1  0  0   = Reference Clock Profile 4
0  1  1   = Reference Clock Profile 3
0  1  0   = Reference Clock Profile 2
0  0  1   = Reference Clock Profile 1
0  0  0   = Reference Clock Profile 0

1   R/W
0 Ref Profile

OK, Building the timing diagram in sections, the next part of the diagram that will be presented is the actual data transfer from the BUS to the Memory.  OK, Adding the DDS and DMA with high speed RAM is a little different than the ADC-CHAN design since we do not have any A/D conversion time to consider.  The process flow diagram is straight forward for this process and is shown below, the data is immediately transferred during the transfer command strobe and the data is on the BUS during that pulse.

Figure 19.5  CPLD #2  DMA Flow Process Timing Diagram #1 Section

From the hardware flow diagram shown in Figure 195 we will create the first pass of the timing diagram that was used to create the DMA section of the CPLD#2 Design.  This timing will generally change as the CPLD#2 is designed and a full timing analysis is performed.  Propagation delays will change with addition to the CPLD when it is compiled.  This is one of the reasons that when using a dual CPLD design one CPLD will handle the critical timing part of a design and remains fixed in order to maintain performance.

Figure 19.5  CPLD #2 DMA Timing Diagram #1 Section

How to Obtain a Finished ITF:
Our plans when the ITF is finished, is to offer an ITF to the public that has many more features than the one being developed for this presentation.  We already have completed two different PoD products to get ready for manufacturing and offering custom development for contract manufacturing companies and the entrepreneur small company that want to setup a development test base for future and present development contracts.  Please use the BASIL Networks Contact Form to be put on a mailing list when we are ready to supply the manufacturing prints if you are interested in purchasing the entire system manufactured and tested.


OK, this is a lot to present in this part and by now we see why the design reuse has merit on stable designs.  Not all designs will survive the reuse environment as we mentioned previously, only about 5% will be a true total Plug'N'Play reuse.  Experience has shown that FPGA and CPLD designs that incorporate the simplest of modifications have the risk of reduced performance, it is the nature of the beast.  

Changing poor engineering habits are difficult however not impossible to correct.  The key is to acknowledge the initial behavior, no it will not change overnight - it took a while to become rooted.  Bringing the development behavior to the surface and acknowledging the behavior is the first step in this series to bring the development process to a winning level.   What this series will present by the successful development of the Core IoT Platform is a winning process to insure success in any project development taken on.

BASIL Networks will be developing educational class room video modules to discuss engineering and project management principles by active example with hardware, software and lab experiments as we continue on with the series.  All hardware and software designed during this series will be available through our on-line video tutorials along with the class materials.

As the series progresses the author, Sal Tuzzo will be available for discussion through the BASIL Networks Contact Form for those that want to apply this series to conduct their own experiments.  I will always be appreciative for the private comments sent through the contact form for suggestions and advice during the development of this series.  This is a growing opportunity for everyone entering into product development as well as a great review for us "well seasoned" in the field to just refresh our human DRAM.

It is recommended for those that have specific questions to use the BASIL Networks Contact Form for questions to separate them from getting lost in the general comments for each blog presentation.  For all specific design request or contracts pleas feel free to contact us.

Part 20+ Preliminary Outline"Design the ITF: -Continued

Reference Links:

ITF Selected Components

BOM Spreadsheet and Component datasheets ZIP file

PGA281 Programmable gain Amplifier Datasheet
IS66WVE4M16EBLL 64Mbit (4M x16) Pseudo SRAM Datasheet
Alliance Memory AS1C8M16PL 128Mbit (8Meg x16) Pseudo SRAM

Intel®/Altera® Quartus Download 9.1 sp2 from Archives
Intel®/Altera® Quartus Lite 18.x Download

Requirements Traceability Matrix  (RTM)
Project Management
Mezzanine Board

The majority of Internet scheme and protocol information are from a few open public information sources on the net, IETF (Internet Engineering Task Force) RFC's that explain details on the application of the protocols used for both IPv4 and IPv6 as well as experimental protocols for the next generation Internet and the Network Sorcery web site.  The remaining of this series on the IoT platform will be from BASIL Networks MDM (Modular Design Methodology) applied with the Socratic teaching method.   Thank You - expand your horizon- Sal Tuzzo

Network Sorcery:
The Internet Engineering task Force: IETF - RFC references

Memory Segmentation
The Memory Management Unit (MMU)
Virtual Address Space
Virtual Addresses and Page Tables
Extended Memory

Previous Part 18 IoT Core Platform - Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Apr 25, 2019)

Next Part 20 IoT Core Platform - Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Mar 23rd, 2020)



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Sal (JT) Tuzzo-Founder CEO/CTO BASIL Networks, PLLC.
Sal is available for client consultation and product development projects
any time by phone, E-Mail, directly through this sites Contact Form or
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