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BASIL Networks BN'B | Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-18

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Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-18

saltuzzo | 25 April, 2019 13:43

Part 18: IoT Core Platform Development;- Peripheral I/O Device Design
The IoT Embedded Core Platform -Peripheral Devices Real World Testing - Continued

"Learning is the beginning of wealth.  Learning is the beginning of health.  Learning is the beginning of spirituality. Searching and learning is where the miracle process all begins."   John Rohn (Sept 17, 1930  - Dec 5th, 2009)

Part 1 Introduction - Setting the Atmosphere for the Series (September 26, 2016)
Part 2 IPv4, IPv6 - The Ins and Outs of IP Internet Addressing  (November 11, 2016)
Part 3 IPv4, IPv6 DHCP, SLAAC and Private Networks - The Automatic Assignment of IP Addressing  (November 24, 2016)
Part 4 Network Protocols - Network, Transport & Application (January 10, 2017)
Part 5 Network Protocols - Network, Transport & Application -Continued (Aug 17, 2017)
Part 6 Network Protocols - Network, Transport & Application -Continued -Ethernet Protocol (Sept 21, 2017)
Part 7 Network Protocols - Network, Transport & Application -Continued -The CRC-32 and Checksums(Nov 23, 2017)
Part 8 IoT Core Platform - SoC Core Processor of Embedded Systems (Jan 12, 2018)
Part 9 IoT Core Platform - SoC Core Processor of Embedded Systems-Vulnerabilities (Mar 16, 2018)
Part 10 IoT Core Platform - SoC Core Processor of Embedded Systems-Product Development Management (Apr 5, 2018)
Part 11 IoT Core Platform - SoC Core Processor of Embedded Systems -Documentation Management Processes (June 27, 2018)
Part 12 IoT Core Platform - IoT Core Platform - Peripherals -Documentation Management Processes (July 29, 2018)
Part 13 IoT Core Platform - Peripheral Interface Devices  -Peripheral Design From the Beginning  (Oct 7, 2018)
Part 14 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design (Oct 29, 2018)
Part 15 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design-Continued (Dec 7, 2018)
Part 16 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design-Continued (Feb 11, 2019)
Part 17 IoT Core Platform - Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Mar 15, 2019)

Quick review to set the atmosphere for Part 18:
To be able to share some wisdom that the author has experienced over the years is part of what mentoring and educations is about.  During the process of product development for a small company verses a large company the differences are in how the resources are managed.  During my career I have been fortunate to have a few mentors that were, as we would say today, not very politically correct.  My mentors were very strong minded and independent scientists and engineers that have been through the "melting pot".  They shared their experiences of designing for manufacturing and that as a design engineer you become part of the product and if an error shows up in manufacturing you are responsible to fix it - period.  That is, you are responsible for your designs throughout the manufacturing process until it is running smooth while maintaining your current project assigned, in simple words - if you designed the product you smooth out any issues to insure a smooth manufacturing process.  Today with outsourcing both design and manufacturing that process is next to impossible to implement for a large company, however for a small company or startup it would be advantageous to insure some in-house expertise so you company is not destroyed for the failure of outside sources to fix.

 Over time designers fell in to the commodity level until recently when true engineering talent became difficult to keep at a company, unfortunately having discussions with corporate managers and engineers the frustration of being tossed around from project to project has taken its tool on talented designers as well as the intense demands on designers today.

OK, as we stated in part 16 we will not be able to cover all the ITF development in a single presentation/part so we will break this down and present the ITF development in a few sequential parts for the series. Just a short change in direction, however a better validation to complete the objective.

From the previous Internet of Things Part-1 through Part- 16 have brought us to this level of what we want in an IoT core Platform.  The real time development process is far from being a linear process from conception to finished product.  Over the past 40 plus years that I have been involved with product design, research, investigations and management so much has changed.

Isolation is the big issue with testing in order to eliminate or reduce interaction the test equipment will have on the Proof of Design build.

Oh, by the way we did mention that we were going to use two CPLD's, the logic will show itself shortly.

What we want to cover in Part 18:
In Part-16 we presented that  fact that we should address testing of the peripherals (Proof of Design) PoD with a prototype build to insure when we interconnect several of the peripherals the throughput required for the applications will be met.  This also put us in a position to change the development direction from the peripheral that we have to developing a test methodology that will be used for testing the remaining peripherals for the platform.  With that stated we will continue moving forward with detailing the Interface Test Fixture (ITF), creating a schematic and PCB layout for the ITF, not all in this part though since it is a relatively large development.  The ITF is a project with multiple sections for testing the IoT Platform and peripherals so we will take perform the development in sections as well.

Updating the IPD project documentation for the Interface Test Fixture to keep track of the development process, "Documentation is a living process during development".   

Several changes have been incorporated for the PoD build and the ITF In-Circuit-Programming Isolated section that we will document for future PoD and manufacture intent builds.

Expanding on the ITF functional block diagram Figure 16.1 the following sections documentation will be created to incorporate into the Interactive Product Development System.

This part will present the Schematic diagrams for the In-Circuit-Programming section for the top five CPLD manufacturers and their proprietary ISP module that we will interface and translate to a single ISP JTAG interface for the ITF.

Lets Get Started:
The IPD Documentation - Developing Documentation Discipline
Remember changing direction overnight does not mean changing goals or the final destination, it is just a better way to insure you will reach them.  In my years of exposure to the design arena as a designer and mentor I have had the honor of experiencing innovative and passionate creators to realize that the thought process of creative passion is not a linear step function, 1, 2, 3 ...N, probably because humans are not robots, that follow a preprogrammed set of processes as some may think.  The innovation of the human mind subconsciously is always performing scenarios to find the best solution for the task at hand.

OK, when we were discussing this project the question came up, Why did you select to use two CPLDs in stead of just on FPGA?  These are the results of that discussion, to review what was stated earlier.  The first reason is we selected MAX line of CPLDs was purely out of the experience level over the years we have used them.  The second reason we selected Intel®/Altera® is the way Altera archives the older revisions of  software on their website, both by date, revision number and the chips supported.  Another factor that weighted it was the amount of resources required to use the latest release of the software of all CPLD/FPGA manufacturers.  

Intel/Altera new release with a 12GB local DRAM would compile the AD-CHAN  MAX-II CPLD OK, however we ran out of memory for the timing diagrams.  All the older releases run on 8GB DRAM/4GB DRAM on the x32 systems easily while the latest release states up to 32GB DRAM or more.  for some of the features.

This would require the majority of small companies and entrepreneurs to purchase the latest and greatest motherboards or desktops that supports that amount of memory.  The majority of older desktop motherboards are limited to 16GB including the Graphics memory and many of the laptops are limited to 8GB that are only a couple of years old.  Another deciding point of using two CPLDs you double the number of I/O pins that should cover this ITF design easily and have some logic Elements to spare for feature expansion and design changes.

OK, a quick review of the documentation system we will be using, Yes again, Ok I'm sounding like management now, - so what does that all mean to this series?  This means that to assist this innovative development process that may change direction at times from one development task to another a tracking system should meet the following requirements.

  1. Interactive - by second nature without thought
  2. Flexibility - being able to record changes and additions in real time.  During development changes in one project can easily effect another project.
  3. Multiple Project Tracking - This is where we are now - being able to start and track new projects that will eventually interact with the product development at hand, hence: the IoT Core Platform development project.
    So, lets give the ITF a Project name- Universal_Peripheral_ITF for lack of a better one.
    AND-- We are going to make some changes, again---

Repetition is the mother of retention,  wait a minute!..., I think I read that somewhere before. :)

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CPLD, FPGA In Circuit Programming Model:
Since we are using CPLDs only on this ITF design we will start at the In-System-Programming (ISP) configuration.  This looks like and generally is a simple connection to program a CPLD on an assembled product however, this becomes more complex when you have several products and test fixtures that you have to maintain and program.  What we have found through experience in the lab is over the years we ended up with over a dozen different ISP programming cables because we just made them up as we needed them and the PCB layout was different for each test fixture we built. Since we did not assign a fixed set of ISP pins each cable was unique and only worked for one design.  We have since then set a standard connector and pin assignment for all CPLD and FPGA designs as we will present.  

Each manufacturer has their own pin assignments for programming their chips with a JTAG or serial protocol that easily translates down to a simple interface connector.  For the JTAG protocol that handles the majority of chips we selected a standard micro six pin connector with a 0603 four resistor isolated SMT for the required pull-up/pull-down terminations.  There are a couple of manufactures that offer the mating connector in a ready made cable that may be plugged into the programming ITF to the UUT.  Considering that the market is now thinning out through M&As this will make it easier to standardize on some interface configurations.  There are other programming modes designed into these devices as well which are used for more complex designs for testing boundaries and other elements within the FPGAs that are not covered in this part of the series since we will not be using any of them.  We will put on the table for discussion creating a new blog series to address FPGAs in the future. The JTAG protocol In-System Programming consists of four signals with the two resource pins which are shown in Table 17.0 below.

We have two types of connectors one for the ITF and one for the production product.  Generally our client selects the programming connector for the production unit that conforms to their in-house connectivity.  For the ITF we selected the standard SATA 7 pin connector since the cables are easily available and the connectors are fairly rugged for many inserts and removals as well as being cost effected, right angle connectors make it easier to interconnect as well.   Using the SATA connectors does change the Standard table assignments that is in Part 17, Table 17.0 which we show the changes in Table 18.0 below Pin Assignment Change in light cyan color and Table 18.1 for all the ISP programmers interconnect assignments.  This is also a change for us in the lab at BASIL Networks as well to upgrade our test system.  We still have the older system to service any obsolete equipment that our clients may still use since some of the Mil Spec requirements require maintainability for 10 years.

For production release ISP connectors, care should to be taken into consideration during the selection process.  The mating connector will be inserted and removed many times, once average for each programming instance.  The ISP connector on the product will see minimum insertion and extraction, however the mating connector will see heavy use.  The ISP connector on the PCB should have an alignment shroud to insure proper alignment during insertion.  We have used Samtec 6, 8 and 10 pin 1.27mm (0.050") pitch shrouded male connectors on the product PCB depending on the type IC's being programmed.  Female header cables are easily purchased through Samtec for a variety of lengths.  The male connector is a better choice for the PCB mainly due to the fact that the female mating header is comparable with flat cable and easily created.

Signal Name Description Pin Assignment Change
TCK  Clock Signal [Data Input] 5
TDI  Data To Device [Data Input] 3
TDO  Data From Device [Data Output] 2
TMS  JTAG machine Stat Control (Enable) [Data Input] 4
Vcc  Vcc Device Power Active Level 1
GND  Signal Ground 6,7

Table 18.0  CPLD  ISP Standard Pin Assignment for ITF Cable Using SATA Connectors

For all PoD assemblies that will see heavy use of the ISP connector we updated the table for the selected SATA 7 pin connector and is shown in Table 18.1 below.

Signal Name Altera 10 Pin Xilinx 14 Pin Cypress  10 Pin Atmel 10 Pin Lattice 10 Pin ITF  SATA 7 Pin
TCk - In 1 6 4 1 1 5
TDI - In 9 10 8 9 5 3
TDO - Out 3 8 6 3 7 2
TMS - In 5 4 2 5 3 4
Vcc 4 2 1 4 6 1
GND 2, 10 3, 5, 7, 9, 11, 13 3, 5, 7, 9 2, 10 2, 4, 8 6,7

Table 18.1   Manufacture ISP Standard Pin Assignment for ITF SATA Cable Pin Assignment

OK, what we find the majority of the time is that the functional block diagram is not the schematic, it is a guide to develop the schematic.  The functional block diagrams purpose is to present an overview of how this device will function.  The schematic irons out the details for actually building a PCB.  

Some additional functionality has been added to the ISP interface which allows the ITF to turn on the ISP connector and well as determine if there is power to the Device being programmed.  This requires an additional Enable and Sense line for each IPS programmer adding an additional 10 CPLD pins to the ITF.  OK so we see how fast pins add up when we start to design.  We already experienced this when designing the AD-CHAN interface with only a single pin to spare and we still have a few functions for the AD-CHAN to address when we get back to the AD-CHAN PoD.  This is another reason the IPD System tracking of multiple projects - yeh, yeh I know, is there a caboose to the documentation train?

The next step is the isolation of the JTAG signal paths which consists of three inputs and one output from Table 18.0.  Generally the JTAG clock rate is dependent on the devices being programmed or tested., however, the clock has a range of 10MHz to 100MHz (100ns to 10ns per bit) and for most CPLD it is 10MHz nominal.  The digital isolation IC we selected is the Analog Devices ADUM241E1WBRWZ  for the 4 channel [3-out/1-in], the single channel isolation IC is the Analog Devices ADUM110N0BRZ both incorporate transformer (3000 volt) isolation methodology

We have a choice of using the UUT power through the ITF ISP connector or adding a separate isolated power supply for the UUT.  It is a good practice to use a separate isolated power supply for the UUT and a separate isolated power supply for the ITF ISP and just use the UUT power to signal the ITF that there is power top the UUT.  The total power for the Isolation side of the ITF ISP is less than 40MA per connector and the ribbon cable short distance less than 24" should work fine.  We are able to get the SN74AHC125N  Tri-state quad buffer in a real DIP package for a standard 14 Pin socket.  This allows for easy repair if the UUT fails.

Figure 18.0a is the updated functional block diagram for a single ISP with the added pins for control.  This will be repeated five times for all the ISP manufacturers we have selected.  For the followers you can change the ISP connector to a manufacturer that is not on the current selection or just make an interface cable to any one of the five ISP channels.

Figure 18.0a   Single Isolated ISP Programmer Interface

Figure 18.0b below shows the schematic of a single channel isolated ISP interface.

OK, some circuit details.  We selected a standard 5 volt supply to handle all the power both non-isolated and isolated.  The isolation takes place, obviously ion the Isolator IC's and when we add that extra enable bit we only needed a single isolator for this.  We also selected to use a separate single isolator IC to separate the JTAG lines from the control lines.  The power sense for the Isolated side is a standard optical isolator that only requires about 10ma at 3.3 volts to activate the output transistor.

The isolators U1 [4 channel] and U3 [single channel] isolate the manufacturers ISP device from the PoD being tested.  The single channel design is repeated with different IPS connectors for the manufacturers selected for this design. The multiple channels allow a single common ground for different manufacturer CPLD's while separating them for the manufacturers ISP to eliminate any interference while testing the PoD device.

The JTAG Standard Terminators RN1 and RN2 are required for both sides of the ISP translator.  When we disable the buffer U2 [74AHC125N] on the isolated side we want be able to set a known steady state for the CPLD device so we may test the PoD without interference from the ISP.

The isolated DC to DC step down 5Vdc to 3.3Vdc, PWR1 has isolation of 1200 Volts and is standard. There are more expensive ones that have 5000 volt isolation breakdown however, 1200V is adequate for our application.

The non-isolated DC-DC step down  5Vdc to 3.3Vdc, PWR6  is a standard buck converter and is available from many sources.

Figure 18.0b   Single Isolated ISP Programmer Interface

The full 5 channel schematic is shown in Figure 18.1 below which we laid out on a double sided PCB 3.9" x 7.0" that we use as a standard in the lab for the majority of our test interfaces.  We use a standard 4"x*'x1.5" standard plastic case for many of our designs when presenting Proof of Design developments.  The design was created using OrCAD capture and layout.

Figure 18.1   Schematic Diagram of the Isolated ISP Programmer Interface

The Layout is very basic and straight forward.  Since all the paths are signal data paths the maximum current for each channel is less than 80ma we do not nee a power and ground plane.  The PCB layout consists of 8mil trace/8mil space for all signal lines and 50mil trace for all power line traces.  8 mil trace / 8 mil space are easily manufactured with a 100% yield.

Figures 18.2, 18.3, 18.4 and 18.5 are the PCB Assembly, Top, Bottom Etch and Fab drawings respectively for the prototype build.

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Figure 18.2   ITF ISP  PCB Assembly Layout

Figure 18.3   ITF ISP  PCB TOP Etch Layout

Figure 18.4   ITF ISP  PCB BOTTOM Etch Layout

Figure 18.5    ITF ISP  PCB FAB Drawing

OK,  this is the first part of the ITF design.  It is a bit too early in the program to make this available to the readers since a prototype has not been built yet.  This part of the ITF design is not a complex layout however, there were times even on the simplest layout errors were made, it is the nature of the beast.  As a rule I do not use the auto routing features in the layout designs.  I prefer to perform the layout by hand using a fixed grid pattern and setting the trace/space parameters to a fixed number.

It is easy to see how product development gets complicated when you bring up testing and Proof of Design.  What makes this interesting for small companies with limited physical resources is the number of hats that each individual is expected to wear to contribute to the companies growth as well as individual growth.  Small companies are a great training ground for engineers and entrepreneurs' and if the company takes off you will obviously see the results of your efforts directly, there will be more opportunities to grow.

The raw material cost for the PCB build:
Creating the Bill of Material (BOM), we use to call this the parts list  The Schematic capture program that is used for this presentation is OrCAD since we are most comfortable with it and have invested heavily in libraries for such.  There are pros's and con's for all of the design packages on the market today.  Some packages allow the full library for components and inventory control, some just give you a schematic name and footprint space and everything in between.  Over the years we developed a method to handle all BOM's for each project and a database library for them that we use for RoHS documents.  What we do also is insure that the data sheet for components used for the design stay with the design at the current revision level for reference.  Since the Internet is constantly changing and documents are added and deleted it is not recommended that the Internet be used as a link to older documents especially if the company is acquired or closed.

So for our approach we actually use a spreadsheet for this since there are both paid licenses and free spreadsheet applications on the Internet, we have used both MS Office and LibreOffice packages and they both work fine and are interchangeable.  Table 18.2 below is our spreadsheet that we use here for the majority of our designs and contains the following columns.  These spreadsheets are saved with the project using the BASIL Networks IPD system that we discussed previously.

Item# DataSheet (Spreadsheet Local File Link) Device Unit Cost
Quantity Solder Profile Device Unit Cost / 100
Reference Designator Package Type Device Unit Cost / 1000
Schematic Value Cad Footprint Required Quantity /100 Build
Description Component Unit Cost Required Quantity /1000 Build
Manufacturer Part Number Component Unit Cost / 100 Buy Total Cost /100 Build
Manufacturer Component Unit Cost / 1000 Buy Total Cost /1000 Build
Distributor Minimum Purchase Required / Component  
Distributor Part Number Lead Time Weeks  

Table 18.2   Common BOM Spreadsheet Column Names

The spreadsheet example Figure 18.6 shown below gives a good picture for management, engineering and manufacturing or any contract manufacturing house selected.

Figure 18.6   ITF   ISP Isolation Interface BOM Spreadsheet

How to Obtain a Finished ISP ITF section:
Our plans when the IoT Core Platform presentation is finished is to offer a finished ITF and the IoT Core Platform to the public that has many more features than the ones being developed for this presentation.  We already have completed two different PoD products that are being reviewed for manufacturing release and we are offering custom development for contract manufacturing companies as well as the entrepreneur small company that want to setup a development test base for present and future development contracts that they are awarded.  Please use the BASIL Networks Contact Form to be put on a mailing list when we are ready to supply the manufacturing prints or if you are interested in purchasing the entire system as a Plug'N'Play.

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The question "why do you want to isolate the ISP device from the manufacturer for the CPLD being programmed?" This question is asked several times and is always a valid question to ask.  The answer that we give here in the lab is from our experiences programming FPGA's and CPLD from different manufacturers and of course the errors that seem to arise during development, we have had our share of destroying ISP devices.  Yah, Yah--- we are experts or at the least well seasoned professionals and those "oops" still happen, it is called human.  In our experience it is very easy to pop an ISP device with the wrong voltages or incorrect hookup or a short on the board that zaps the ISP device.  Isolation allows the repair of the isolated output and protects the ISP from the manufacturer as well as being very cost effective.

The other question that was asked several times, is it possible to program the CPLD JTAG connections with an alternative programmer?  The simple answer is yes,there are programmers that allow programming several manufacturers devices other than the manufacturers ISP device.  The complicated answer is why would you want to when the CPLD, FPGA manufacturer gives you an ISP device programmer and software designed for their chips?  It is not only time saving but advantageous to use a manufacturers ISP device for validation since the validation of the device has already been proven reliable.  Added to the answer is each manufacturer has their own coding ID for each chip being programmed along with variations in the security bits to lock the device.

The direction of this blog has been developing from the conception and the direction has taken a few turns, however the objective is still the same, to develop an IoT Core Platform.  The directions are apparent that this is an educational blog and the end result is that we will offer the product to the public to continue on with several applications development projects that will encourage entrepreneur's to innovate and apply the knowledge taught here to develop new products on their own.

BASIL Networks will be developing educational class room video modules to discuss engineering and project management principles by active example with hardware, software and lab experiments as we continue on with the series.  All hardware and software designed during this series will be available through our on-line video tutorials along with the class materials.  Figures 18.0 through 18.5 are an example of the product design tutorials that will be presented as the IoT Platform series moves forward.  It is not advised to copy these presented designs since the finished product will be tested, validated and available as we complete each sections PoD.

As the series progresses the author, Sal Tuzzo will be available for discussion through the BASIL Networks Contact Form for those that want to apply this series to conduct their own experiments.  I will always be appreciative for the private comments sent through the contact form for suggestions and advice during the development of this series.  This is a growing opportunity for everyone entering into product development as well as a great review for us "well seasoned" in the field to just refresh our DRAM.

It is recommended for those that have specific questions to use the BASIL Networks Contact Form for questions to separate them from getting lost in the general comments for each blog presentation.  For all specific design request or contracts please feel free to contact us.

Part 19+ Preliminary Outline" A/D Channel Hardware/Software Design and the ITF: -Continued

  • Reviewing the IPD Documentation System
  • Creating the Schematic for the ITF
  • Creating the PCB Layout for the ITF
  • PCB FAB drawings and ordering the ITF for this series.
  • A link to download the IBPD System for this series.
  • A review or the Successive Approximation algorithm used in A/D conversion
  • Testing the A/D peripheral.
  • Adding other features to the A/D Channel while finishing the PoD schematics for the ITF
  • And more ....

Reference Links for Part 17:

ITF Selected Components

BOM Spreadsheet and Component datasheets ZIP file

PGA281 Programmable gain Amplifier Datasheet
IS66WVE4M16EBLL 64Mbit (4M x16) Pseudo SRAM Datasheet
Alliance Memory AS1C8M16PL 128Mbit (8Meg x16) Pseudo SRAM

Intel®/Altera® Quartus Download 9.1 sp2 from Archives
Intel®/Altera® Quartus Lite 18.x Download

Requirements Traceability Matrix  (RTM)
Project Management
Mezzanine Board

The majority of Internet scheme and protocol information are from a few open public information sources on the net, IETF (Internet Engineering Task Force) RFC's that explain details on the application of the protocols used for both IPv4 and IPv6 as well as experimental protocols for the next generation Internet and the Network Sorcery web site.  The remaining of this series on the IoT platform will be from BASIL Networks MDM (Modular Design Methodology) applied with the Socratic teaching method.   Thank You - expand your horizon- Sal Tuzzo

Network Sorcery:
The Internet Engineering task Force: IETF - RFC references

Memory Segmentation
The Memory Management Unit (MMU)
Virtual Address Space
Virtual Addresses and Page Tables
Extended Memory

Part 1  Introduction - Setting the Atmosphere for the Series (September 26, 2016)
Part 2  IPv4, IPv6 - The Ins and Outs of IP Internet Addressing (November 11, 2016)
Part 3  IPv4, IPv6 DHCP, SLAAC and Private Networks - The Automatic Assignment of IP Addressing (November 24, 2016)
Part 4  Network Protocols - Network, Transport & Application (January 10, 2017)
Part 5  Network Protocols - Network, Transport & Application Continued (Aug 17, 2017)
Part 6  Network Protocols - Network, Transport & Application Continued-The Ethernet Protocol(s) (Sept 21, 2017)
Part 7  Network Protocols - Network, Transport & Application Continued-The CRC-32 and Checksums (Nov 27, 2017)
Part 8  IoT Core Platform& Development
- Embedded Processor Systems-(SoC)-(SIP) Core Processor -Embedded System Configurations  (Jan 12, 2018)
Part 9  IoT Core Platform Development - Embedded Processor Systems-(SoC)-(SIP) Core Processor -Embedded System Configurations (Mar 16, 2018)
Part 10 IoT Core Platform - SoC Core Processor of Embedded Systems-Product Development Management (May 5, 2018)
Part 11 IoT Core Platform - SoC Core Processor of Embedded Systems -Documentation Management Processes (June 27, 2018)
Part 12 IoT Core Platform - IoT Core Platform - Product Design  -Creating Conceptual Design Documentation (July 29, 2018)
Part 13 IoT Core Platform - Peripheral Interface Devices  -Peripheral Design From the Beginning (Oct 7, 2018)
Part 14 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design (Oct 29, 2018)
Part 15 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design-Continued (Dec 7, 2018)
Part 16 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design-Continued (Feb 11, 2019)
Part 17 IoT Core Platform - Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Mar 15, 2019)

Publishing this series on a website or reprinting is authorized by displaying the following, including the hyperlink to BASIL Networks, PLLC either at the beginning or end of each part.
BASIL Networks, PLLC - Internet of Things (IoT) -Security, Privacy, Safety-The Information Playground Part-17 Peripheral I/O Design - Peripheral Devices- Real World Testing - (Mar 15, 2019)

For Website Link cut and paste this code:

<p><a href="" target="_blank">BASIL Networks, PLLC - Internet of Things (IoT) -Security, Privacy, Safety-The Information Playground Part-18 Peripheral I/O Development:-<i>Real World Testing (April 25, &nbsp;2019)</i></a></p>

Sal (JT) Tuzzo-Founder CEO/CTO BASIL Networks, PLLC.
Sal is available for client consultation and product development projects
any time by phone, E-Mail, directly through this sites Contact Form or
through LinkedIn


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