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Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-16 | BASIL Networks Blog BN'B

11 Feb, 2019

Internet of Things (IoT) Security, Privacy, Safety -Platform Development Project Part-16

Part 16: IoT Core Platform Development;- Peripheral I/O Device Design
The IoT Embedded Core Platform -Peripheral Devices Real World Testing - Continued

"Entrepreneurs are never satisfied. They want to do things better. They strive for perfection and use all the ingenuity to their command to achieve it." - J. W.  Mariot (Sept 17, 1900  - Aug 13, 1985)

For those that are interested in the stages of a design engineers life and mindset they are from birth to 10 years of age generally defined as "Stubborn ",  from 10-21 years of age generally defined as "Thick headed", from 21-40 years of age generally defined as "Strong Minded" and 40 years and older is defined as "Seasoned".  The Authors mindset is well seasoned. Cool


Quick review to set the atmosphere for Part 16:
From the previous Internet of Things Part-1 through Part- 15 have brought us to this level of what we want in an IoT core Platform.  It has also brought us awareness of the needs for privacy, security and control of devices attached to the Internet and how easy it is to intercept various protocols and change data being transferred over the information highway.  From all the data breaches being published on a daily basis we see that the original design of the Internet had and still has a couple of shortcommings.  One shortcomming is .... wait for it!  We will be designing security into the IoT Platform from the start and not as an after thought to be added later.

Now that the basic idea and some of the different aspects of product development have been introduced, it is a good practice to document ideas and concepts as well as additions using the IPD system.  Using the RTM section to insure that as we develop each section there are guidelines and test cases to insure that all the pieces fit together.  The basic features incorporated into the IPD system are:

Technology has advanced at a rapid rate over the past 50 years that it becomes difficult to keep up with the technology, however what is interesting is the level of common knowledge has also increased by the use of the technological advancements.  This series is presenting some of the advancements that are no common knowledge to be applied as we all do with common knowledge, without a second thought to benefit from the application to explore other areas and repeat the process.   Our intent is to make the peripherals interfacing common knowledge to be easily applied to any core processor and perform functions to experiment and collect data to advance science.

What we want to cover in Part 16:
At this time the IoT Core Platform is a universal platform that may be applied to many infrastructure critical applications as well as commercial simple applications.  Prior to the selection of the Core Processor some real world I/O is generally a requirement to all applications for real world communications.

A quick detour to present some of the new component developments since we started the series.  We will then get back into the analog input development and present some details of why we picked the Analog Input Peripheral as the first I/O development project.

More of the RTM for the Interactive Product Development System, OK,Yes-developing good engineering documentation habits comes with the territory, documentation is still in the picture and still important.  

Setting up Requirements Traceability Matrix (RTM) for the test cases for the analog input.  Traceability during development covers all aspects from Business, Legal as well as Technical and is essential when validating each stage of the project.  We will keep this more at a technical project development, PoD (Proof of Design) level for a while until we get to a point where the business side is required.

We will answer questions sent in from our readers about the design.

Lets Get Started:
The IPD Documentation - Developing Documentation Discipline
It is always beneficial to review the documentation process being used to keep the our development processes organized and to review the areas that have not been completed, not that we have to complete them in any order.  It is a mind-set encouragement task for the section currently being developed.  The mind of the passionate creator is not a linear step function, 1, 2, 3 ...N, probably because humans are not robots, that follow a preprogrammed set of processes.  The innovation of the human mind is always performing scenarios to find the best solution for the task at hand.

OK, so what does that all mean to this series?  This means that to assist this innovative development process a tracking system should meet the following requirements.

  1. Interactive - by second nature without thought
  2. Flexibility - being able to record changes and additions in real time.  During development changes in one project can easily effect another project.
  3. Multiple  Project Tracking - being able to start and track new projects that will eventually interact with the product development at hand.

Repetition is the mother of retention Cool

The Peripheral Assignments Set:
From when this series started till present day there have been several new Interface IC's introduced to the market that we should review with the expectation of reducing development time and of course adding new features that would leverage our market share, yes, we always keep in mind the "monetization" of our development.

We looked at the AD7124-8 temperature IC a while ago however they just released a update to the IC April; 2018.  This chip will allow 8 channels of temperature sensing with a typical sampling rate of 25 Samples Per Second per channel for a full 24 bit dynamic range.  The device is full integrated with  a 24 bit Sigma-Delta A/D converter along with a PGA all synchronized by the internal SCLK of 614.4KHz.  It is a one chip solution on a 32 pin LFCSP (Lead Frame Chip Scale Package) basically a flat-pack with pads on the bottom of the chip instead of pins on each side.   There is some support circuitry that is generally required, however for our application we would update the SPI input requirements to add a separate channel for this device.  The cost / performance makes this chip a good choice.  We will cover this when we get to that part of the peripheral design.

One of the questions that was submitted by a reader, Why not just use one of these chips for the Analog Input?  OK, the answer to put this to rest is that they are all low speed A/D converters and when you put a multiplexer in the front end you slow down the individual channel throughput by (A/D Samples/Second) ÷ (Number of Channels) along with no buffer.  Many of these chips are less than a megasample per second.  

The Analog Input Design Continued:
OK, so from the Part-15 we see that there is only one spare pin on the 100 pin CPLD and if we want the full 22 gain ranges available on the PGA we have to use the last spare pin on the CPLD.  So should we go to the next package up, the 144 pin?  Some history - when we designed this peripheral several years ago and released the design one pin extra was not an issue since we only had one of four gain ranges and that only took 2 pins as well as only having a one Meg x16 buffer so we had some pins to spare.  The new design incorporates new features which takes up more pins so to start do we want the full 22 gain ranges, the answer is yes, more gain ranges gives better windowed resolution of the input signal.  The cost differential for a 100 pin to a 144 pin is about 2x the cost increase, the FPGA is about 3 times the cost, however there is more flexibility as well with the FPGA than the CPLD.  This does not just end here, there are other avenues that we will address when we start to look at the other peripherals development and if there are spare pins on the FPGA for the several digital serial inputs to handle other types of sensor chips.

To show just how fast technology changes during a product development cycle, when we started this design the largest cost effective SRAM available was one Meg x16. Shortly after that the Pseudo SRAM was introduced as 2 Meg x16, shortly after about 12 months that size went to 4 Meg x16. The next generation and size was introduced in August 2018 by Alliance Memory, a 8 Meg x16 Pseudo SRAM.   Now the challenge comes with the way the addresses are setup to write/read the data, the first 16 bits are Address/Data multiplexed and the remaining addresses 16..21 are fixed.  There are other timing considerations to using a multiplexed address/data memory device for our A/D Channel design that we will cover later on in the series.

This means that it is not a true parallel asynchronous SRAM where address and data are separated.  So if  we want to add an additional 4 meg x16 with a single chip we have to redesign the CPLD to accommodate the access requirements or we can just add an additional 4 Meg x16 chip and it will only cost us one control line which at this time does not exist in the CPLD if we keep the 22 gain ranges.  The cost differential is relatively low enough as to go with two chips verses one, however there is a cost to assembling the boards since costs are directly proportional to the number of components that have to be mounted.  The FPGA or the 144pin CPLD is leveraging up to be selected.  Lets continue on.

The leverage with this design is that it has a older PoC and PoD that we pulled out of our design library for "reuse".  If this was not the case then the recommendation would be to build it separately as a single channel to evaluate and test the PoD (Proof of Design).  OK, entrepreneurs do not contradict themselves they just adjust the design to be better and since this is an educational series we will build the PoD.  It is always a good practice to build a PoD production intent or otherwise unless the circuit is so simple it would not be required, however when using CPLD's and FPGA's it is always a good practice to build a PoD engineering model to iron out component issues as well as manufacturing issues.  Performing a Schematic and Layout also gives a foundation of the actual size requirement for a single channel, the number of PCB layers that will be required, shielding of sensitive signals and impedance control traces etc. requirements.

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Should We Just Go With The FPGA For The PoD Module?
Using an FPGA and combining several of the peripherals in a single chip with out doubt gives a better cost breakdown per peripheral, however what we usually find is we get back into the same category that the embedded processor market is in by trying to add as many peripherals to the chip and then pin sharing.  Pin sharing also reduces access and throughput timing as we read from the data sheets of these devices.  Granted FPGA's with enough pins will be similar to a real PC BUS and allow full access in both DMA and Interrupt configurations to time slice the peripherals at the top speed of the BUS.  We are not ruling out the FPGA for the final pre-production run however, for the educational series we will go with the PoD build concept this time.  As we gain experience in building the platform we would then select the peripheral schema for the application and probably just jump into a FPGA and run.  Keep in mind that if this is a device that requires a strong security protocol then the manufacturing process mechanically has to be taken into perspective to insure physical tampering is blocked from getting the internals of the FPGA code.

What Will The PoD Module Cost?
The cost for the PoD build varies depending on the security to protect the design.  If this is a DoD classified design then the rules for building have to be approved by the DoD and a vetting process has to take place.  If this is a commercial not classified design then to protect the design to a relative level a local PCB fab house that you have done business with and established a trust relationship with fits the plan.  Below is a list of materials for the PoD build using the 100 pin CPLD that interfaces to a eight bit port for testing.  Here in the lab we use the IBPD (Interactive BUS Protocol Development) system since we have been putting it together for a while for this purpose.  It also gives us the flexibility to measure performance of the Analog input PoD.  OK, the price disclaimer! The estimated cost for the PoD is taken from the Internet from Octopart which in many cases lists several distributors, this in no way is an approval of any company or advertisement, it is for educational purposes only.  Every company has their own supply chain management mechanism in place and should price this accordingly.  The unit cost for a single PoD is under $100.00. not including the PCB.  We purchase 5 boards at a time from several Fast PCB fab houses in the USA for the commercial non-classified projects, that is about $150.00 door to door for a 4"x7" PCB 2 sided. and about $300.00 door to door 4-layer.  Any sizes below that would not be much less since the major portion of the pricing is labor and machine time.  This also allows space for additional experimentation added chips like the FPGA or Amplifiers.  The estimated material cost for the PoD single channel is under $150.00 with 4 PCBs to experiment with at a later time.  Our library for this design is a quad channel Analog input card with address and control expansion capability build in.

Adding A Real World Interface On PoD and Validation Modules:
The Schematic of the Analog Input Module has to be completed for the PoD by adding some type of interface to the real world to test it.   Well we are at the point to decide to use a standard desktop, laptop or embedded processor interface to test the peripherals we will be designing.  There are pros and cons in all designs and it is best to Keep It Simple and Save (KISS) method. Of course the last S has several words depending if the first attempt really failed and you want to make a point. Cool  

Here is the authors point of view that has evolved over the years since each of these have been experimented with during the many development projects.  There is no "silver bullet" to guarantee the success of any development, even working from a working model.  When you transfer the design from a PoD to an actual production intent there are always issues to address.  The issue with any development is to be able to segment the different parts of the design and test them to get an empirical data of the devices input/output characteristics. This allows you to perform a system analysis on the performance as well as to interface to other devices and systems.  

Interface Test Fixture Pro's/Con's Summary:
OK now that we see there is no easy way to address testing the PoD without some type of a custom interface.  Wireless was not mentioned as an approach mainly due to security, all test fixtures connected use a wired interface.  When we test wireless it is in a shielded area to maintain a fixed perimeter.   Ok, we easily see the pros and cons of the above approaches, however of all of them connecting to the main analysis desktop or laptop a wired network would be an advantage since we can collect data in the lab and do analysis in an office area or another area outside the lab.  USB devices have been banned in may secure areas and the IT department that maintains the controlled area PC's disable the interface in the OS to insure that they will not function if plugged in.   We are looking at a specific PCIe laptop ExpressCard interface card for Laptops specifically for the IBPD system.  The ExpressCard interface for a laptop allows much easier mobility for the next generation of the IBPD system.   Since the IBPD does include internal buffer memory the network interface would be the selected choice since all PC's today come with some type of internal network that may be hard wired.

OK, a bit of engineering marketing for BASIL Networks, PLLC - The IBPD system has a High Speed parallel I/O feature with a buffer, however it is only a couple of meg x16 bits at 10ns throughput.  So to address many of the peripheral requirements of the IoT Platform the IBPD system main controller will be undergoing a hardware update for this blog series.  The update will be a buffer from a single channel of 2 Meg x16 to a dual channel 16 bits each capable of 4 Meg x32 expandable to 64 meg x32 at 10ns throughput rate.  This will address the 32 bit processor series that we are also looking at for the IoT Platform.  The Engineering experience, it is easy to build one or two or even 10 of just about anything however, building 10,000 requires a stable design and project traceability and testing during development.

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BASIL Networks Approach to Interface Test Fixtures:
Through the years of product development we have experienced many setbacks with special or custom interface test fixtures for the products we were contracted to develop.  The issue that stood out the most was the setup and repeatability of test when we were requested to make requested revisions to the design.  Prior to the changes we would setup the test to insure we were at a stable starting point prior to the revisions.  Well, this did create some issues since the test fixtures were as common as could possibly be and used for other projects.  The fixtures were also updated over time and when we set it up to repeat the testing of a previous product, well the results were different.  This directed us to question the definition of what our in house test system should incorporate to increase the quality of our product development, Reliability, Repeatability, Functionality and Time saving (R2FT) is what every test system should inherently be.  This brought us to the level of what it would take to develop a test system that allows a simple custom interface that may remains with the initial product development used for validation.  Using a fixed test interface fixture and keep it with the PoD products we were able to demonstrate the R2FT methodology.  To date we were able to develop inexpensive test interface fixtures connected to the IBPD system and maintain complete one step Plug'N'Play repeatability to the validated PoD and Production models.  We were able to keep the cost of the typical Interface Test Fixture (ITF) under $250 with standard connectors and maintain this with the product PoD and validation hardware.   We have found that non-standard connectors specified by some clients are very expensive, however, the cost of non-repeatable test results when having to setup a test with different hardware can easily exceed those costs.  This bring us to the Interactive Product Development (IPD) system that is part of the stable repeatability and P'N'P test setup, all development documentation and test documentation remain in a single accessible location.   OK, enough of the marketing sales pitch, lets put this together with real hardware designs.

What we came up with is an isolated digital interface that is capable of interfacing up to 64 bits data and 24 bits control capable of speeds up to 10ns capture and control through an FPGA and CPLD on board to any specified connectors since this board stays with the product development any connectors the customer desires may be implemented.  A functional block diagram of the test setup segments are shown below.

We will be designing several peripheral interfaces and it would be advantageous to have a general purpose test fixture to be able to just plug the peripheral in and test the design and performance throughput.  There will always be some sort of independent test fixture to test devices in development, this comes with the territory.  It is one of the areas that I have experienced in the 35 plus years designing products for manufacturers that is neglected "AND" ends up costing more time and money to fix issues that crop up during manufacturing.  Test fixture design is as important as the product you are designing and has to be addressed.  The difficulty is that it is better to address this during the development and with some innovation one can development a interface test fixture that will handle many different functions.  Hence: that is what our intent is here at this time.  It is one of the reasons we selected the Analog Input peripheral as the first peripheral to design.  From Figure 12.3 IoT Platform Interface Function Segment Mapping  that shows the different peripherals that we want to incorporate into the platform a Interface test fixture would be an advantage.   So, lets put together a functional block diagram with a little innovation that would make it easier to test these peripherals.  From the beginning we selected to use a parallel BUS architecture to communicate with the core CPU in order to get the maximum throughput from the processor as well as being able to incorporate DMA (Direct Memory Access) for the processors main core memory.

Figure 16.0  PoD  Interface Test Fixture  Block Diagram

The schematic for the ITF will include both an FPGA and/or a CPLD - The selection of the FPGA is with the Intel/Altera® Cyclone series and the CPLD is the MAX II, MAX10-FPGA series.  Any FPGA and CPLD series like Xilinx® etc. may be substituted if that is what the designer is more comfortable with.  The interface logic design is just aligning the right pins to functions within the FPGA and CPLD to meet the expectations of the PoD device.  For this series we selected the QFP (Quad Flat Pack) case outline mainly because it may be repaired in house manually. For pin assignment we have a 144 QFP (89 I/O pins ) the CPLD is similar for I/O Pins and the QFP's are standard packages.  The initial design used the Cyclone FPGA which is obsolete and was selected because it used a 240 pin QFP.  The devices available in a QFP seem to stop at 144 pins and limited to a smaller series.  Using BGA's requires an outside assembly house to assemble and repair if necessary so keeping this as an in house build for the entrepreneur and small company seems appropriate for an educational series. The FPGA is MAX 10 10M08SCE144A7G  with 101 I/O and will handle from 1.25V I/O to 3.3 V I/O to cover all the types of interface devices.  The FPGA is MAX 10 10M08SCE144A7G  with 101 I/O and will handle from 1.25V I/O to 3.3 V I/O to cover all the types of interface devices.  The programmable logic device market share has been changing with the Microchip acquiring Atmel and Intel acquiring Altera and Xilink and Lattice Semi holding it's own.  The CPLD's and FPGA's we used several years ago are no longer available and since the M&A's the inventory is also thinning out.  This means it would be a good practice to use some of the modern IC's for the test fixture.  We also looked at Quartus Prime Lite - the memory requirements will work for many if we use the MAX II or V series and would work with about 2 to 4 GB RAM.  If we go to the higher FPGA's we would need up to 32GB RAM, yes- 32GB RAM.  This puts many students and beginners outside the resources available at this time.  We even run older systems here that have a max of 16BG RAM allowed on the main board.  

The ITF  PoD Device Interconnects:
For those who were curious on why we picked the Analog Input peripheral to start, well it has the most interconnections and the most components external to the FPGA and/or  CPLD which ever we select as the final production device.   The original reuse Analog Input device was originally designed over 10 years ago incorporating a byte wide I/O BUS using a parallel 16 bit SAR A/D converter and 65535 x16 static RAM buffer.  So we modified this design a few years ago to accommodate the updated embedded processor market and added a much larger buffer.  With that stated this is a good time to discuss just what type of peripheral BUS architecture we want to have on the IoT Core Platform.  Yes, we did discuss this before and selected the 8 bit BUS architecture to get things moving along, however since this is a new development project we do have options to change as we develop, that is what development is all about- being able to adjust to the times.  Many embedded processors have a 32 bit core with a varying I/O BUS architecture, 8/16/32 to address many applications.

Since we separated the I/ O Peripherals from the core CPU and decided to make adding the peripherals P'N'P devices as required by the application hence, a micro version of a desktop where we just plug in a peripherals or connect them via a BUS connectors or cable or even wireless to the Core CPU.  Interconnecting the variety of peripherals now requires us to address the core CPU I/O BUS interconnect scheme and how we are to test the performance of any peripheral added.

The Interface Test Fixture (ITF) interconnectivity is a critical part of a successful product development and it is one that the industry always tries to risk manage out of the picture building test system due to the time and expense involved.  For all us seasoned designers we have learned not to lose any sleep over it however we do insure that accountability for the SNAFU of testing is assigned appropriately.

We have to decide on the type of connector to put on the ITF to accommodate peripherals.  Our intent is to be able to create any type of peripheral that may be connect to any embedded core CPU type.  The embedded market is changing and there are many types of embedded systems out there to choose from.  The market is also thinning out as we discussed to make room for the next generation.  The M&A transition always happens prior to the next generation of technology in order to filter out the players that are not interested in staying in the game.  So as designers we have to remain as flexible as possible to remain in the competition and avoid the headaches of redesigning a product due to obsolescence.  As we stated in the previous parts, peripherals are best kept separate for the embedded system in order to take advantage of the changing embedded CPU technologies.  The other advantage is that sensor and input devices by design have a longer life time cycle in the industry than CPU's of processors and address the embedded market arena naturally.

OK, to start the ITF interconnection design expectation is that it will handle 8/16/24/32 bit high speed data transfers, so we can leave the design as is or as an option increasing the peripheral I/O to a 16 bit BUS architecture for the core CPU instead of the eight bit byte architecture.  While we are at this level and the design is still just a paper design lets investigate the pros and cons of increasing the I/O BUS width from eight bits to 16 bits.  There are a few questions that arise immediately with this investigation of change.

So before we go off on a tangent lets just look at the throughput required to transfer the entire four Meg buffer into the CPU core memory for analysis or just transferring the data to the real world over the network  The typical assumption of a network data transfer is that the processor and memory runs an order of magnitude faster than the network traffic at least for the desktop and Laptop devices, Our IoT Platform core CPU expectations is that it will have at least a 200MHz clock rate and a 100MHz from side memory BUS.  The process is to just transfer the four meg x16 A/D Channel memory into a core CPU accessible memory in order to transfer it over the network, thus making the A/D channel ready to collect more analog input data.  

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OK, collecting data a the maximum sample rate of one microsecond would take four seconds to fill the four Meg x16 buffer.  Here is where some internal understanding of the architecture of the selected embedded core processor is required.  All embedded processors are not created equal, all for silicon equal rights :).

The process of transferring I/O to core CPU accessible memory does have similar process steps which are 1. Read I/O port memory data,  2. Move I/O data to core CPU memory.  This requires at least two full data transfers and in some embedded systems three to four depending how the I/O architecture is characterised, so lets take the worst case four steps.  For a 200MHz core CPU the I/O instruction time would be about 40ns per instruction, therefore 40ns x 4 instructions = 160 ns per memory location resolves to 4,194,304 x 160 x10-9 = 0.6711 seconds.  This time would at least double for an 8 bit BUS I/O architecture.

So that means that we may collect four meg x16 blocks of data every 0.7 seconds for a 16 bit I./O architecture or 1.4 seconds for an eight bit I/O architecture on average until we run out of local core memory.  Transferring four meg x16 bits of data in a stream protocol over the Ethernet will take at least .7 seconds to transfer each word to the Ethernet controller plus the time to transfer each word through the network and acknowledge the transfer.

So the question is will a maximum of .7 or 1.4 seconds for a block of 4 Meg x16 be sufficient for the majority of application? Or another way to ask, how many real world applications would that throughput fit or fail?  We have time to think about this and look up some IoT control applications.  Either way we should look at a 16/32 bit I/O ITF interconnect to characterize the performance at the full speed of the peripheral.

The Interface Test Fixture:
At this point we are able to understand how the development of  "test equipment" can get out of hand especially if the test system requires additional custom interface software and other special development.  This is one of the reasons that management looks at a risk management approach when it comes to test fixtures.  Over the years we have been on both ends of the track when developing test equipment especially when the validation requirements adds cost to the test fixture to prove the validation requirements approach and sometimes exceed the cost of developing the product being tested.  

OK, it is not all that bad says the optimist Cool, it really is not that bad.  Technology advancements have made it possible to create test equipment with a new philosophy that we will present here which is what we use here is our solution to test fixtures we use during product development that is inexpensive enough to actually keep the ITF with the product development for the duration of the products life even after it enters production.  The expectations of the ITF for this series is to be capable of collecting validated data for analysis to insure the features and functions of the Unit Under Test (UUT) meets the design and marketing performance.  

Today's test interconnects are mainly data collections mechanisms for off-line data analysis, unless the analysis is capable of being performed within the ITF.  So, to eliminate the risk management equation, we are presenting a methodology that we have used here for many years which we have incorporated into a  test system that is programmable, inexpensive and flexible to interface any test fixture.  This is the Interactive BUS Protocol Development (IBPD) System that we presented earlier in the series for the entrepreneur and manufacturer can incorporate into their development strategy for a cost effective product development mechanism.

To give this series a better purpose we have decided to integrate a COTS USB interface with a special driver for the IBPD to be used for the Interface Test Fixture for all the peripherals being developed in this series.  The basic IBPD core is available for download at this time and the intent is to have the IBPD driver for the ITF ready for download by the next few parts of the series along with the FPGA and CPLD configuration files prior to the building of the PCB for the ITF.  OK, keep in mind that the ITF is a product development and we have a choice of making it part of this IoT Platform project or creating a separate project.  The choice for us would be to make the Interface Test Fixture a separate IPD project for reuse since it will end up as a universal test fixture for many other projects down the road.  

OK, another marketing plug; Running multiple projects with the Interactive Product Development (IPD) system keeps track of all the details of each project and allows us to interactively manage document changes in real time.  Wow - too many acronyms, well there are not that many new ones however, we will put a list together for this series in the summary for reference throughout the series.

Creating The ITF Hardware:
The ITF PCB at this time does not exist for this series, so for a sense of reality in the product development environment we will develop the ITF in line with the PoD Analog Input peripheral.  Designing a new product is challenging, designing in testability is even more challenging since the Interface Test Fixture becomes part of the product design responsibilities.  Who better to design the ITF than the individual that designed the product!  We have other test fixtures here in the lab so we would not be starting from scratch.  Figure 16.1 ITF Test Setup Block Diagram below shows our expectations and what we will be putting together for the IoT Peripherals ITF.

Focusing on the first peripheral development PoD interconnects selecting a connector set to interface the PoD is important since it has to meet the speed requirements of the peripheral in order to validate throughput expectations. For this design series we selected the old industrial standard IDC ribbon connector, they are inexpensive and readily available, we have used these type cables at speeds up to 10ns for short runs of shielded flat cable.  We will design the ITF interconnection connectors for a 8/16/32 bit I/O system and complete the pin assignment for the PoD PCB.  The 144 Pin TQFP FPGA and CPLD interconnects to the isolation block should be sufficient to handle just about any type of peripheral communications between peripherals and the IBPD System.  Since this is going to be used to test a variety of peripherals incorporating a buffer memory on the ITF would be a good to test full speed performance of the Unit Under Test (UUT).

Since we are addressing high speed performance with the ITF incorporating a high speed static RAM in the 8ns to 10ns speeds are suggested since they are readily available in four to 16 megabyte sizes and are COTS.  This does sound like an over-kill, however it is a one time cost and if you build one for engineering development and one for manufacturing the product transfer to production will be much smoother and increase the quality of manufacturing especially when a good reference is available to shorten production test times.  Our Analog PoD schematic will move towards completion when we get the ITF interconnects completed.

OK, it is easy during the development process to go on tangents and lose focus on the product. That is one of the reasons companies have an engineering department and a test equipment department, oh FYI - that does not guarantee success of the product and in larger companies engineering test fixtures take a back seat to manufacturing production test fixtures.  Our approach covers both the development and manufacturing which may be automated to start on demand as well as having separate test scripts for each manufacturing stage.

Figure 16.1  ITF Test Setup Block Diagram

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Wow, here we were thinking we would just design the Analog Input peripheral and be done.  As we see test equipment plays a key roll in the performance testing and validation for the peripherals.  Test equipment development is a project in itself and should be done in parallel with the product development to insure all the test performance issues are covered.  This does entails parallel development of the ITF however, with the IBPD system methodology we should only have to design the initial ITF interconnectivity once to cover all the remaining peripherals.  Test equipment interconnects main function is to test all functions of the product and of course collect data for performance analysis.  

There are still a few more sections for the Analog Input peripheral that has to be completed which we will cover in the next part of the series.  What we have been able to accomplish to date is a solid ground floor understanding of how the IoT peripheral devices are to be configured to the core CPU.  The selection of the Analog Input device is a good start to understand how peripherals are configured and controlled regardless of the type of BUS interface used to communicate with the host CPU.

We will without doubt come back here as we build and test this peripheral.  Development is not a simple smooth road in a technology environment that is constantly changing and offering more flexibility and features a few time a year.  We have be ale to address this rapidly and implement changes within a competitive time range to obtain a market share.

Keeping track of multiple projects methodically and allowing interaction to update in real time is a challenge the has been addressed in the lab over the years that evolved into an Interactive Product Development (IPD) System.  No fancy names or complex software gymnastics, just a simple effective, efficient tool to assist the designer(s) through product development stages.

All companies have some sort of management development system, however for those that realize that their system is not able to handle the growing demands, call us to talk about tailoring our IPD and IBPD system to meet your needs.  Each part of this development series demonstrates the advantages of interactive development tools as the IBPD and the IPD system as we implement these tools for each stage of the IoT Platform development stages. All functions neatly organized in the appropriate folders with a easy Click'N'Open access to organize and track the development process.  

As the series progresses Sal will be available through the BASIL Networks Contact Form for discussions for those that want to apply this series to conduct their own experiments.  I want to thank all the readers for their comments of encouragement and letting me know their appreciation for this publication.

Part 17+ Preliminary Outline" A/D Channel Hardware/Software Design and the ITF: -Continued

Reference Links for Part 16:

PGA281 Programmable gain Amplifier Datasheet
IS66WVE4M16EBLL 64Mbit (4M x16) Pseudo SRAM Datasheet
Alliance Memory AS1C8M16PL 128Mbit (8Meg x16) Pseudo SRAM

Intel®/Altera® Quartus Download 9.1 sp2 from Archives
Intel®/Altera® Quartus Lite 18.x Download

Requirements Traceability Matrix  (RTM)
Project Management
Mezzanine Board

The majority of Internet scheme and protocol information are from a few open public information sources on the net, IETF (Internet Engineering Task Force) RFC's that explain details on the application of the protocols used for both IPv4 and IPv6 as well as experimental protocols for the next generation Internet and the Network Sorcery web site.  The remaining of this series on the IoT platform will be from BASIL Networks MDM (Modular Design Methodology) applied with the Socratic teaching method.   Thank You - expand your horizon- Sal Tuzzo

Network Sorcery:
The Internet Engineering task Force: IETF - RFC references

Memory Segmentation
The Memory Management Unit (MMU)
Virtual Address Space
Virtual Addresses and Page Tables
Extended Memory

Part 15 IoT Core Platform - Peripheral I/O Development - Analog Input Peripheral Device Design-Continued (Dec 7, 2018)

Part 17 IoT Core Platform
- Peripheral I/O Development - Peripheral Device Real World Testing -Continued(Mar 15, 2019)


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Sal (JT) Tuzzo - Founder CEO/CTO BASIL Networks, PLLC.
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