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GENERAL SPECIFICATION AND CONCERNS OF THE  SEQUENCER INSTRUMENT DURING DEVELOPMENT The sequencer instrument is a product that I developed at BASIL Networks several years ago and just keeps on popping up with new applications. The key to any device of this type is the ability to deliver high speed digital signals in the 5 to 10 ns period range. The successful design will incorporate high frequency layout rules that are directly related to the designers packaging. Hence: change the packaging changes the design and layout.  The sequencer is basically a cache memory controller with the data ports feeding the real world, sounds simple enough, though, many tried few succeeded at a high cost.  Designing an accurate 200 MHz pipeline counter without the prop delays getting in the way is a little bit easier today with CPLD's but they still require some know how.  There have been some changes to this design to accommodate the testing of the bridge circuit and driving the modules six switching devices.  Driving High-Low MOSFETs required the design of a isolated drive circuit to insure that the threshold voltage, (Vth) is guaranteed. The other additions is the OFF State latch. This latch is basically a holding current latch for all three phases which will turn the devices on to a certain current level in each phase and not change. That is to say it will PWM to a specific point on the wave form being generated and remain in that state. The summary page will explain this in more detail.  The addition of a multiplexor was added to allow multiple PWM patterns to be switched in/out for comparing different PWM schemes without changing the test setup. Memory expansion is not as important today as it was 10 years ago. The density of high speed cache is now in the 36 meg bit (2Meg x 18 bits,  1Meg by 36 bits) and have speeds in the 3.5 to 10 ns range and are much less expensive.  The addition of a few timers for controlling the on/off intervals of the PWM waveform without the need for processor support, allows this device to free run and generate synchronization signals for other instruments. We selected this sequencer to control the triggering of all other attached devices because this is where the main bridge control signals are generated and monitored by the attached control computer. Also added was an external connector allowing the user to design and attach their own bridge driver design. This design has taken several forms of the past several years, from dedicated Open Bus Interface Architecture (OBIA), to an ISA interface. I am looking into a USB design as a stand alone instrument that if any one is interested they should contact me JT for product specifics. This design generally travels with me from contract to contract requiring a fast system development.

3Ø BRIDGE TEST SYSTEM  -  SEQUENCER INSTRUMENT SECTION BLOCK DIAGRAM For a larger picture click on the image To explain the actual application and some of the limitations of PWM generation and control, we will look at the default setting of this system. To start we look at the memory width as an eight bit playback state per point. That is each address has eight bits that are programmable to any state. The memory's depth is 18 bits allowing 262,144 locations. The playback system is controlled by a final address register allowing playback control from a start location to a final location. The direction is also controlled as from a final location to a start location or from a start to the final location, hence bi-directional. The maximum rate at which the eight bit width is played backed at is determined by the speed of the memory chips, in this case it is 10ns, 100MHz. The new design is capable of  a 5 ns, 200 MHz playback rate and the latest proprietary designs have rates of up to 1ns. The playback is programmable up to the highest speed via a playback register. Now how does all this apply to the bridge module and PWM ? A detailed explanation is also given in the Test System Presentation PDF file (4 Meg file) downloadable from the first page of this TDA.,  A simple explanation is as follows. A simple sinewave may be generated as Asin(Ø). Where "A" being the amplitude from min to max and Ø being the angle from 0 to 360°.  Now what we would like to do is control the amplitude "A" for any point on the 360° period. Since we are generating this waveform digitally the amplitude resolution of each point along the X axis is determined by the number of steps we are able to resolve its amplitude "A" to. If we use 10 steps then we will have 10 unique amplitudes to relate to which is represented as A(i)/10 * sin(Ø). where i=0,1...9.  This covers the amplitude section. Now if we are to break the X axis up into 360 steps then we would get 1° per digital point. that would be resolved to an amplitude of one part in ten. Looking at this we see that we may get the same vertical value for several points on the sinewave, giving us almost a stepped waveform.  When we apply this to an motor as explained in the PMB DC Motor analysis this becomes a performance issue. Our default values of this test setup are 1000 parts for the vertical "Y" resolution and this number determines the number of points for the X axix. This means that for every X point we would require 1000 points to determine the Y value for a PWM point. Since we are controlling the FETs driving some sort of load configuration, the PWM point only supplies the power to the load for the number of pulses that resolve the vertical "Y" amplitude from 0 to 1000 pulses that set 0 to 100% of the point. The amplitude of the waveform becomes the duty cycle/   Each point is in this case is 1000 addresses wide allowing the FET to be turned to deliver power to the load in 0.1% steps. What does this mean in terms of maximum waveform period ? Well, if we playback the memory at 50 nanoseconds per address, and there is 1000 address per point then each point would be at 50 microseconds. Since this design uses only 265,144 locations, a 260 point waveform fits into the memory easily. This yields 260 points at 1000 steps vertically for each point for a total of 260,000 addresses. Playing this back at 50 nanoseconds per address then the total sinewave period is 260,000 * 50 nanoseconds or 13 milliseconds, 76.923 Hz. Applying this to a PMB two pole motor we would get a maximum speed of 4615 RPM. If we lowered the vertical resolution we would be able to increase the RPM. for a 10ns playback rate this system is capable of a 2.6 millisecond period, 384.615 Hz. therefore applying this to a six pole PMB motor we would get a maximum speed of 7692 RPM, (60* 384.615 / 3) This would allow the motor to be tested at any speed up to the maximum. or drive reactive loads as transformers for digitally controlled 3Ø variable voltage and variable frequency power supplies. I will be adding a section on PWM generation and analysis as time permits explaining how to mathematically optimize the vertical and horizontal resolutions for the best performance for the application. Now that we explained this with the least of mathematics, the PMB Motors  TDA will explain more of the theoretical analysis using MathCAD for this application.

        

EIGHT CHANNEL DC TO RMS AND PEAK DETECTOR CIRCUIT Measuring the PWM load current of an inductive load along with any strange peaks that may occur as well as the RMS values has always been interesting to say the least. To start with I collected data at a relatively fast rate in comparison to the playback period of 13 milliseconds. For this test I used both very expensive current probes and inexpensive COTS hall effect current modules.  The modules specifications guaranteed a full scale frequency response of 60KHz at ±100 amps which when tested turned out to be within 0.5%  vertical accuracy and a frequency response beyond 100KHz and beyond that for small 10 amp transients at 80 amps base line. The hall sensors used had a 3 MHz bandwidth and the amplifier was the main limiting factor with a 1 MHz unity gain bandwidth. If I were to design one today I would expect the highest bandwidth that could be manufactured  These sensors produced a DC voltage of ±5Vdc full scale for the 100 Amp device, 20 amps per volt. and ±10 Volts for the 400 Amp device, 40 amps per volt.  Our data acquisition system  that sensed the current was capable of 300,000 Samples / Second at 16 bits vertical resolution along with a programmable gain amplifier per channel. This allow us to resolve around a 1 milliamp at 100 amps, well within anything this application would require. Measuring peak and rms levels were done in hardware and not software to maintain a single data collection rate for all the testing as well as making the data collection simple. We used a 500 MHz bandwidth digital scope to monitor transients and load current as shown in the summary.  A dedicated system for this field would be an asset to the future advances in PWM power drivers and we would be interested in advancing this field of interest. BASIL Network offers its expertise in the system development services in this area for those interested.

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