Advances in the manufacturing of power semiconductors has benefited from the lithography technologies of microprocessor development. This advancement of less than 1 micron lithography has allowed brought the manufacturing of very low Rds ON power semiconductors. These enhancements brought us to the level where it is now possible to manufacture semiconductors and mount them directly on to some form of substrate, eliminating single die packaging. This is the areas we will be addressing in this presentation of Power Modules and Hybrids. One of the main applications of these power modules is the driving of a Permanent Magnet Brush less (PMB) DC motor. PMB DC Motors are now being used in a variety of applications in the automotive industry as well as in the automated testing industry to name a couple. This technology is expected to experience a large increase in applications as the PMB DC motor technology improves and is marketed.

There are fundamentally two types of three phase H-bridge modules on the market today, ones with an integrated current sense component and ones without. Since the majority of the bridge circuits are power MOSFETs or IGBTs, biasing these in a Hi-Lo configuration becomes a challenge. Some of the main considerations of a test system follows. Since the semiconductors used are very low Rds ON devices, turning both on at the same time is a guarantee burnout as observed in the circuit below. Therefore, one of the main parameters that we have to identify is the break-before-make time of the upper and lower device, commonly known as the DEAD TIME. The next consideration is the biasing of the Hi-Lo drive circuit, which also has to guarantee the dead time throughout the operating temperature range. Generally this intermediate drive circuit is very close to the semiconductors and would most likely be thermally cycled with the module under test. The next parameter is the total power this module has to deliver to the reactive load which brings us to the a parameter called DC loop resistance. This DC loop resistance contributes directly to the losses in the circuit and the drive capability to the load. By simple loop analysis if the loop resistance is equal to the load resistance then the maximum voltage at the load is 1/2 of the applied voltage to the loop. The figures below show a typical bridge circuit and the current carrying paths. The one we chose for this test has an integrated current sense resistor.

TYPICAL 3Ø PHASE H-BRIDGE CIRCUIT & INTEGRATED CURRENT SENSE

This diagram below shows the current carrying paths of the bridge circuit. The ideal layout would be for all phase current paths to have identical impedance characteristics thus eliminating the phase balance problem that typically surfaces with these circuits. This is explained in the PMB Motor analysis TDA

TYPICAL 3Ø PHASE H-BRIDGE CIRCUIT CURRENT PATHS USED for TRACE LAYOUT

SINGLE PHASE DUTY CYCLE
ONE POINT OF THE PWM WAVEFORM 2 PERIOD

The timing diagram below represents one point of the total waveform generated using a three phase PWM scheme which is discussed later in this TDA. The duty cycle of each point is calculated for each phase pair of the waveform. The DEAD TIME between the upper and lower FET devices prevents a short circuit across the bridge power during the phase switching transitions. Without this DEAD TIME there would be high current spikes (Vbat/Rds-ON) that would cause component failure. The following chapters focus more on how we control these modules with a sequencing instrument which is part of the test system. However keep in mind that the dead time is one of the most important areas of the application of these types of modules. The majority of thermal problems occur when the dead time is too small a value. Empirical and theoretical data for a variety of power MOSFETs shows a dead time of approximately 400-nanoseconds for a temperature span of 75 °C referenced to 25 °C ambient to be within the SOA. Other SOA for this type of bridge will vary with ambient cooling techniques used to extract the heat from the devices. The dead time is contributed to a number of FET switching parameters to allow enough time for the FET to turn completely off.

%Duty Cycle = ( Ton ÷ Tp ) • 100

MODULE HEAT SINK  MOUNTING CONFIGURATION
CERAMIC MODULE MOUNTED WITH ADHESIVE

The mounting of the bridge module to a thermal heat sink to allow adequate heat extraction is also a major concern.  In this case, shown below, we have a ceramic module that requires some type of adhesive mounting materials to ensure thermal conductivity. The figure also shows thermocouple attachments throughout the mounting layers. This is the way the thermal stack is analyzed for this particular module and test. If this was an encapsulated module we would be measuring the case to heat sink only, because we would not be able to access the semiconductor devices. The following chapter will discuss the data collection mechanism that any analysis of the data. Other manufacturing techniques of these devices actually use a metal lead frame and look almost like the current trace diagram above. There are many ways to manufacture these modules and I am sure that there will more to come as the technology matures. Heat extraction is also a very important design requirement. Many of these modules will require some type of air flow around the heatsink to insure heat extraction. This adds to the challenges of incorporating these device into your application.

DC ELECTRICAL EQUIVALENT CIRCUIT of the LOOP RESISTANCE COMPONENTS

As we stated, Loop Resistance and phase to phase balancing are two more difficult parameters to maintain. Both contribute directly to the efficiency of the bridge circuit. At high power levels, milli-ohms make a big difference that is measurable at the load device. When physically laying the bridge circuit out, care has to be taken with the conductive material such that the interconnects for the semiconductors have very little losses or impurities. The diagram below shows all the elements of resistance within the loop itself. In this example we show a ceramic substrate which typically incorporate six power transistor die directly soldered to the substrate and interconnected by bond wires bonded to the top of the die making the phase pair. This is a typical scheme that is used throughout the industry but not without its problems. Bond wires also add resistance to total loop impedance as well as connection integrity issues depending on the bond wire size and type of bond applied. The loop resistance for the design used here was very low, less than 10 milli-ohms to the modules connection points and less than 25 milli-ohms when incorporated into some sort of control electronics and lead frame. The total loop resistance therefore, dictates that a minimum of a 25 milli-ohm DC load resistance be used in order to yield a maximum drive voltage to the load of Vbat ÷ 2, which directly relates to power efficiency and module power dissipation. There are other contributing electrical and mechanical factors that also add to the loop resistance which are not covered in this article and will be covered in future articles on designing three phase bridges. Above we displayed the current carrying traces of the bridge which also is an ideal layout for phase balancing and low loop resistance. The test system's capability also allows the measurement and data gathering of some of these internal resistance components of the substrate by allowing control of individual devices within the substrate. The figures below show the DC equivalent circuit and the mechanical connection system using bond wires. An analysis in MathCAD has been developed during each of the design phases of this test system and will be referenced throughout the TDA.

LOOP ANALYSIS EQUIVALENT MODEL CURRENT PATH PHASE B to PHASE C
This model would be repeated for all three phase combinations, AB,BC,CA